The user may trade off throughput for power consumption by
simply performing fewer conversions per unit time. The
Power Consumption vs. Sample Rate curve in the Typical
Performance Curves section shows the typical power con-
sumption of the ADC104S021 versus throughput. To calcu-
late the power consumption, simply multiply the fraction of
time spent in the normal mode by the normal mode power
consumption, and add the fraction of time spent in shutdown
mode multiplied by the shutdown mode power dissipation.
Applications Information (Continued)
5.0 ANALOG INPUTS
An equivalent circuit for one of the ADC104S021’s input
channels is shown in Figure 5. Diodes D1 and D2 provide
ESD protection for the analog inputs. At no time should any
input go beyond (VA + 300 mV) or (GND − 300 mV), as these
ESD diodes will begin conducting, which could result in
erratic operation.
The capacitor C1 in Figure 5 has a typical value of 3 pF, and
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the multiplexer and track / hold switch, and is
typically 500 ohms. Capacitor C2 is the ADC104S021 sam-
pling capacitor, and is typically 30 pF. The ADC104S021 will
deliver best performance when driven by a low-impedance
source to eliminate distortion caused by the charging of the
sampling capacitance. This is especially important when
using the ADC104S021 to sample AC signals. Also important
when sampling dynamic signals is a band-pass or low-pass
filter to reduce harmonics and noise, improving dynamic
performance.
7.1 Power Management
When the ADC104S021 is operated continuously in normal
mode, the maximum throughput is fSCLK/16. Throughput
may be traded for power consumption by running fSCLK at its
maximum 3.2 MHz and performing fewer conversions per
unit time, putting the ADC104S021 into shutdown mode
between conversions. A plot of typical power consumption
versus throughput is shown in the Typical Performance
Curves section. To calculate the power consumption for a
given throughput, multiply the fraction of time spent in the
normal mode by the normal mode power consumption and
add the fraction of time spent in shutdown mode multiplied
by the shutdown mode power consumption. Generally, the
user will put the part into normal mode and then put the part
back into shutdown mode. Note that the curve of power
consumption vs. throughput is nearly linear. This is because
the power consumption in the shutdown mode is so small
that it can be ignored for all practical purposes.
7.2 Power Supply Noise Considerations
The charging of any output load capacitance requires cur-
rent from the power supply, VA. The current pulses required
from the supply to charge the output capacitance will cause
voltage variations on the supply. If these variations are large
enough, they could degrade SNR and SINAD performance
of the ADC. Furthermore, discharging the output capaci-
tance when the digital output goes from a logic high to a logic
low will dump current into the die substrate, which is resis-
tive. Load discharge currents will cause "ground bounce"
noise in the substrate that will degrade noise performance if
that current is large enough. The larger is the output capaci-
tance, the more current flows through the die substrate and
the greater is the noise coupled into the analog channel,
degrading noise performance.
20124414
FIGURE 5. Equivalent Input Circuit
6.0 DIGITAL INPUTS AND OUTPUTS
The ADC104S021’s digital output DOUT is limited by, and
cannot exceed, the supply voltage, VA. The digital input pins
are not prone to latch-up and, and although not recom-
mended, SCLK, CS and DIN may be asserted before VA
without any latch-up risk.
7.0 POWER SUPPLY CONSIDERATIONS
To keep noise out of the power supply, keep the output load
capacitance as small as practical. If the load capacitance is
greater than 50 pF, use a 100 Ω series resistor at the ADC
output, located as close to the ADC output pin as practical.
This will limit the charge and discharge current of the output
capacitance and improve noise performance.
The ADC104S021 is fully powered-up whenever CS is low,
and fully powered-down whenever CS is high, with one
exception: the ADC104S021 automatically enters power-
down mode between the 16th falling edge of a conversion
and the 1st falling edge of the subsequent conversion (see
Timing Diagrams).
The ADC104S021 can perform multiple conversions back to
back; each conversion requires 16 SCLK cycles. The
ADC104S021 will perform conversions continuously as long
as CS is held low.
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