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ADC08832

更新时间： 2024-01-02 04:27:25
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德州仪器 - TI /
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31页 1546K
描述
8-Bit Serial I/O CMOS A/D Converters with Multiplexer and Sample/Hold Function

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ADC08832 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：SOP, SOP14,.4Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.68最大模拟输入电压：5.05 V
最小模拟输入电压：-0.05 V最长转换时间：4 µs
转换器类型：ADC, SUCCESSIVE APPROXIMATIONJESD-30 代码：R-PDSO-G14
JESD-609代码：e0长度：9 mm
湿度敏感等级：2A模拟输入通道数量：2
位数：8功能数量：1
端子数量：14最高工作温度：85 °C
最低工作温度：-40 °C输出位码：BINARY
输出格式：SERIAL封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP14,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：220电源：5 V
认证状态：Not Qualified采样速率：0.153 MHz
采样并保持/跟踪并保持：TRACK座面最大高度：2.65 mm
子类别：Analog to Digital Converters标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.5 mmBase Number Matches：1

ADC08832 数据手册

 浏览型号ADC08832的Datasheet PDF文件第1页浏览型号ADC08832的Datasheet PDF文件第2页浏览型号ADC08832的Datasheet PDF文件第3页浏览型号ADC08832的Datasheet PDF文件第5页浏览型号ADC08832的Datasheet PDF文件第6页浏览型号ADC08832的Datasheet PDF文件第7页 
ADC08831, ADC08832  
SNAS015C –SEPTEMBER 1999–REVISED MARCH 2013  
www.ti.com  
Electrical Characteristics (continued)  
The following specifications apply for VCC = VREF = +5VDC, and fCLK = 2 MHz unless otherwise specified. Boldface limits  
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.  
Symbol  
IOUT  
Parameter  
Conditions  
Typical(1)  
Limits(2)  
Units (Limits)  
TRI-STATE Output Current  
VOUT = 0V  
−3.0  
3.0  
μA (max)  
μA (max)  
VOUT = 5V  
VOUT = 0V  
VOUT = VCC  
ISOURCE  
ISINK  
Output Source Current  
Output Sink Current  
−6.5  
8.0  
1.0  
2.4  
1.8  
3.5  
mA (max)  
mA (min)  
mA (max)  
mA (max)  
mA (max)  
mA (max)  
ICC  
Supply Current ADC08831 CLK = VCC CS = VCC  
CS = LOW  
0.6  
1.7  
1.3  
2.4  
ICC  
Supply Current ADC08832 CLK =  
CS = VCC  
(8)  
VCC  
CS = LOW  
(8) For the ADC08832 Vref is internally tied to VCC, therefore, for the ADC08832 reference current is included in the supply current.  
Electrical Characteristics  
The following specifications apply for VCC = VREF = +5 VDC, and tr = tf = 20 ns unless otherwise specified. Boldface limits  
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.  
Symbol  
Parameter  
Conditions  
Typical(1)  
Limits(2)  
Units (Limits)  
fCLK  
Clock Frequency  
2
MHz (max)  
Clock Duty Cycle(3)  
40  
60  
% (min)  
% (max)  
TC  
Conversion Time (Not Including MUX  
Addressing Time)  
fCLK = 2MHz  
8
4
1/fCLK (max)  
μs (max)  
tCA  
Acquisition Time  
½
1/fCLK (max)  
ns (min)  
tSET-UP  
CS Falling Edge or Data Input  
Valid to CLK Rising Edge  
25  
tHOLD  
Data Input Valid after CLK  
Rising Edge  
20  
ns (min)  
tpd1, tpd0  
CLK Falling Edge to Output Data Valid(4)  
CL = 100 pF:  
Data MSB First  
Data LSB First  
250  
200  
ns (max)  
ns (max)  
t1H, t0H  
TRI-STATE Delay from Rising Edge  
of CS to Data Output and SARS Hi-Z  
CL = 10 pF, RL = 10 kΩ  
(see TRI-STATE Test Circuits and  
Waveforms)  
50  
ns  
CL = 100 pF, RL = 2 kΩ  
180  
ns (max)  
pF  
CIN  
Capacitance of Analog Input(5)  
Capacitance of Logic Inputs  
Capacitance of Logic Outputs  
13  
5
CIN  
pF  
COUT  
5
pF  
(1) Typicals are at TJ = 25°C and represent the most likely parametric norm.  
(2) Specified to TI's AOQL (Average Outgoing Quality Level).  
(3) A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle  
outside of these limits the minimum time the clock is high or low must be at least 250 ns. The maximum time the clock can be high or  
low is 60 μs.  
(4) Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in to allow  
for comparator response time.  
(5) Analog inputs are typically 300 ohms input resistance to a 13pF sample and hold capacitor.  
4
Submit Documentation Feedback  
Copyright © 1999–2013, Texas Instruments Incorporated  
Product Folder Links: ADC08831 ADC08832  
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