Dynamic Characteristics
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The following specifications apply for VCC 5V, fCLK 2MHz, TA 25˚C, RSOURCE 50Ω, fIN 45kHz, VIN 5VP, VREF 5V,
non-coherent 2048 samples with windowing.
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
fS
Sampling Rate
ADC08831
ADC08832
fCLK/11
fCLK/13 (Note 21)
181
153
ksps
ksps
SNR
Signal-to -Noise Ratio (Note 19)
Total Harmonic Distortion (Note 20)
Signal-to -Noise and Distortion
Effective Number Of Bits (Note 18)
Spurious Free Dynamic Range
48.5
−59.5
48.0
7.7
dB
dB
THD
SINAD
ENOB
SFDR
dB
Bits
dB
62.5
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed speci-
fications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance character-
istics may degrade when the device is not operated under the listed test conditions.
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Note 3: All voltages are measured with respect to GND 0 V , unless otherwise specified.
DC
<
>
V ,) the current at that pin should be limited to 5 mA. The 20
CC
Note 4: When the input voltage V at any pin exceeds the power supplies (V
IN IN
(GND) or V
IN
mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T , θ and the ambient temperature, T . The maximum
JMAX JA
A
=
allowable power dissipation at any temperature is P
(T
JMAX
− T )/θ or the number given in the Absolute Maximum Ratings, whichever is lower.
D
A
JA
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor. The machine mode is a 200pF capacitor discharged directly into each pin.
Note 7: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or Linear Data Book section “Surface Mount” for other methods of soldering
surface mount devices.
=
Note 8: Typicals are at T
25˚C and represent the most likely parametric norm.
J
Note 9: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Total Unadjusted Error (TUE) includes offset, full-scale, linearity, multiplexer errors.
Note 11: It is not tested for the ADC08832.
Note 12: For V
IN(−)
≥ V the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Functional Block Diagram) which will
IN(+)
forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than V supply. During testing at low V levels (e.g., 4.5V), high
CC CC
level analog inputs (e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors for analog inputs near full-scale. The
spec allows 50 mV forward bias of either diode; this means that as long as the analog V does not exceed the supply voltage by more than 50 mV, the output code
IN
will be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 V to 5 V input voltage
DC DC
range will therefore require a minimum supply voltage of 4.950 V
DC
over temperature variations, initial tolerance and loading.
Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following two
cases are considered: one, with the selected channel tied high (5 V ) and the remaining off channel tied low (0 V ), total current flow through the off channel is
D
C
D
C
measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channel is again measured. The two cases con-
sidered for determining on channel leakage current are the same except total current flow through the selected channel is measured.
Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits
the minimum time the clock is high or low must be at least 250 ns. The maximum time the clock can be high or low is 60 µs.
Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in to allow for comparator re-
sponse time.
Note 16: For the ADC08832 V is internally tied to V , therefore, for the ADC08832 reference current is included in the supply current.
ref CC
Note 17: Analog inputs are typically 300 ohms input resistance to a 13pF sample and hold capacitor.
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Note 18: Effective Number Of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB (SINAD-1.76)/
6.02.
Note 19: The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included in it’s calculation.
Note 20: The contributions from the first 6 harmonics are used in the calculation of the THD.
Note 21: The maximum sampling rate is slightly less than f /11 if CS is reset in less than one clock period.
CLK
5
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