by connecting the second input on each capacitor and open-
ing all of the other switches (S switches). The change in volt-
age at the inverter’s input, as a result of the change in charge
on each input capacitor, will now depend on both input signal
differences.
1.0 Functional Description (Continued)
ladder for the A/D as well as for generating the DAC signal.
The DAC output is actually the tap on the resistor ladder
which most closely approximates the analog input. In addi-
tion, the “sampled-data” comparators used in the ADC0820
provide the ability to compare the magnitudes of several
analog signals simultaneously, without using input summing
amplifiers. This is especially useful in the LS flash ADC,
where the signal to be converted is an analog difference.
1.2 THE SAMPLED-DATA COMPARATOR
Each comparator in the ADC0820 consists of a CMOS in-
verter with a capacitively coupled input (Figures 6, 7 ). Ana-
log switches connect the two comparator inputs to the input
capacitor (C) and also connect the inverter’s input and out-
put. This device in effect now has one differential input pair.
A comparison requires two cycles, one for zeroing the com-
parator, and another for making the comparison.
DS005501-12
=
• V
V
B
=
O
• V on C V1−V
B
=
=
• C
stray input node capacitor
inverter input bias voltage
S
B
• V
Zeroing Phase
In the first cycle, one input switch and the inverter’s feedback
switch (Figure 6 ) are closed. In this interval, C is charged to
the connected input (V1) less the inverter’s bias voltage (VB,
approximately 1.2V). In the second cycle (Figure 7 ), these
two switches are opened and the other (V2) input’s switch is
closed. The input capacitor now subtracts its stored voltage
from the second input and the difference is amplified by the
inverter’s open loop gain. The inverter’s input (VB') becomes
FIGURE 6. Sampled-Data Comparator
DS005501-13
and the output will go high or low depending on the sign of
VB'−VB.
The actual circuitry used in the ADC0820 is a simple but im-
portant expansion of the basic comparator described above.
By adding a second capacitor and another set of switches to
the input (Figure 8 ), the scheme can be expanded to make
dual differential comparisons. In this circuit, the feedback
switch and one input switch on each capacitor (Z switches)
are closed in the zeroing cycle. A comparison is then made
Compare Phase
FIGURE 7. Sampled-Data Comparator
DS005501-45
DS005501-14
FIGURE 8. ADC0820 Comparator (from MS Flash ADC)
1.3 ARCHITECTURE
after at least 600 ns, the output from the first set of compara-
tors (the first flash) is decoded and latched. At this point the
two 4-bit converters change modes and the LS (least signifi-
cant) flash ADC enters its compare cycle. No less than 600
ns later, the RD line may be pulled low to latch the lower 4
data bits and finish the 8-bit conversion. When RD goes low,
the flash A/Ds change state once again in preparation for the
next conversion.
In the ADC0820, one bank of 15 comparators is used in each
4-bit flash A/D converter (Figure 12 ). The MS (most signifi-
cant) flash ADC also has one additional comparator to detect
input overrange. These two sets of comparators operate al-
ternately, with one group in its zeroing cycle while the other
is comparing.
When a typical conversion is started, the WR line is brought
low. At this instant the MS comparators go from zeroing to
comparison mode (Figure 11 ). When WR is returned high
Figure 11 also outlines how the converter’s interface timing
relates to its analog input (VIN). In WR-RD mode, VIN is mea-
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