®
®
ADC-674
12-Bit, μP-Compatible A/D Converter
PERFORMANCE (TYPICAL, CONT.)
Differential Linearity Error ➃
Bipolar Offset, max. ➄
0.5LSB
0.1ꢀ of FSR
10 ppm/°C
Unipolar Offset max.
Bipolar Offset max.
Tempco: ➇
10 ppm/°C
Full Scale Calibration max.
10 ppm/°C
+V = 13.5V to 16.5V or +11.4V to +12.6V max.
s
0.001ꢀFSR/ꢀV
Power Supply Rejection: ➈
V
= +4.5V to +5.5V max
logic
Footnotes:
➀ Available for external loads. External load should not change during conversion.
When supplying an external load using a +12V supply, a buffer amplifier must be
provided for the reference output.
➁ Logic Inputs - CE, CS, R/C, A0, 12/8.
➂ Logic Outputs - DB11-DBO, STS.
➃ Over temperature.
➄ Adjustable to zero.
➅ With 50 Ω fixed resistor from REF OUT to REF IN. Adjustable to zero.
➆ No adjustment at 25°·C.
➇ Guaranteed maximum change, Tmin to Tmax (using internal reference).
➈ Maximum change in full scale calibration.
TECHNICAL NOTES
1. The ADC-674 may interface directly to a microprocessor which can take
full control of each conversion, or the device can be operated in the "stand
alone" mode (controlled only by the R/C input). Full control consists of
selecting an 8- or 12-bit conversion cycle, initiating the conversion and
reading the output data when ready. The data may be read 12 bits at once
or 8 followed by 4 in a left-justified format. There are five control inputs
(12/8, CS, A0, R/C: and CE) and all are TTL/CMOS compatible. (See Control
Input Truth Table.)
these input resistors may change 400 mV with each bit decision, causing
sudden changes in current at the analog input. Therefore, the signal source
must maintain its output voltage while supplying these step changes in load
current which occur at 1.6 microsecond intervals. This requires low output
impedance and fast settling by the signal source.
5. The power supply used should be low noise and well regulated. Voltage
spikes can affect accuracy. If a switching supply is used, the outputs should
be carefully filtered to assure "noise free" dc voltage to the converter.
Decoupling capacitors should be used on all power supply pins; the +5V dc
2. A conversion is initiated by a logic transition on any of the three inputs: CE,
CS, R/C. One, two, or all three may be dynamically controlled. The nominal
delay for each of the three inputs is the same and if necessary, all three
may change states simultaneously. If it is required that a particular input
controls the start of conversion, the other two should be set up at least 50
nanoseconds earlier. (See Start Convert Timing, Figure 3).
supply decoupling capacitor should be connected directly from +V
(Pin
logic
1) to digital common (Pin 15). V (Pin 7) should be decoupled directly to
cc
A
(Pin 9). It is recommended that a 10 μF tantalum type in parallel with
GND
a 0.1 μF ceramic type be used for decoupling.
6. The use of good circuit board layout techniques is required for rated
performance. It is recommended that a double sided printed circuit board
with a ground plane on the component side be used. Other techniques,
such as wirewrapping or point-to-point wiring on vectorboard will have an
unpredictable effect on accuracy. Sensitive analog signals should be routed
between ground traces and kept away from digital lines. If analog and
digital lines must cross, they should do so at right angles.
3. To read the output data, four conditions must be met (or the output buffers
will remain in high impedance state): R/C taken high, STS low, CE high and
CS low. When this is accomplished, the data lines are activated according
to the state of the 12/8 and A0 inputs. (See TIMING DIAGRAM on Figure 4).
4. The analog signal source driving the ADC-674's input will see a nominal
load of 5 KΩ (10V range) or 20 KΩ (20V range). However, the other end of
DATEL
•
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
•
Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
20 Jan 2012 MDA_ADC-674.A02_D3 Page 3 of 7
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