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ADC-674L/883 PDF预览

ADC-674L/883

更新时间: 2022-12-01 21:22:49
品牌 Logo 应用领域
村田 - MURATA /
页数 文件大小 规格书
7页 193K
描述
A/D Converter, 12-Bit, 1 Func, CQCC28,

ADC-674L/883 数据手册

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®
®
ADC-674  
12-Bit, μP-Compatible A/D Converter  
Interface To An 8-Bit Data Bus  
CE  
CS  
The 12/8 input will be tied either high or low in most applications. With 12/8  
high, all 12 output lines become active simultaneously for interface to a 12- or  
16-bit data bus. A0 is ignored. Taking 12/8 low organizes the output in two 8-bit  
bytes, which are selected one at a time by A0. This allows an 8-bit data bus to  
be connected as shown below. A0 is normally tied to the LSB of the address  
bus for storing the converter's output in two consecutive memory locations.  
This two byte format is called "left justified data" for which a decimal point  
is assumed to the left of byte 1. In addition, A0 may be toggled at any time  
without damage to the converter. Break-before-make switching is guaranteed  
between two data bytes, which assures that the outputs strapped together as  
shown are never enabled at the same time.  
tSSR  
tHSR  
tHRR  
R/C  
A0  
tSRR  
tSAR  
tHAR  
STS  
tHD  
tHS  
HIGH  
DATA  
VALID  
DB11-DB0  
IMPEDANCE  
tDO  
tHL  
Figure 4. Read Cycle Timing  
ADDRESS BUS  
ADC-674 TIMING  
3
5
6
28  
STS  
Symbol  
Parameter, Read Mode  
Access Time from CE  
Min.  
-
Typ.  
-
-
Max.  
150 nS  
CS  
R/C  
CE  
A0  
DB11 (MSB)  
4
2
27  
26  
25  
24  
23  
t
t
DD  
DB10  
DB9  
DB8  
DB7  
Data Valid after CE low  
Output Float Delay  
CS to CE Setup  
25 nS  
-
-
HD  
12/8  
t
-
120 nS  
HL  
t
t
t
t
50 nS  
0
0
0
-
-
SSR  
SRR  
SAR  
R/C to CE Setup  
A0 to CE Setup  
-
ADC-674  
DATA  
BUS  
50 nS  
0
-
DB6  
DB5  
22  
21  
20  
19  
18  
17  
16  
Valid after CE Low  
CS  
0
0
-
0
HSR  
HRR  
HAR  
t
t
RIC High after CE Low  
A0 Valid after CE Low  
STS Delay after Data Valid  
0
0
-
DB4  
0 nS  
30 nS  
DB3  
t
-
300 nS  
HS  
DB2  
DB1  
DB0 (LSB)  
Symbol  
Parameter, Read Mode  
STS Delay From CE  
CE Pulse Width  
Min.  
-
Typ.  
Max.  
200 nS  
DGND  
15  
t
-
-
-
-
-
-
-
-
DSC  
t
t
50 nS  
50 nS  
50 nS  
50 nS  
50 nS  
0
-
-
-
-
-
0
-
HEC  
SSC  
HSC  
SRC  
HRC  
CS to CE Setup  
t
t
CS Low during CE High  
R/C to CE Setup  
Figure 5. 8-Bit Data Bus Interface  
t
R/C Low during CE High  
A0 to CE Setup  
t
SAC  
t
A0 Valid during CD High  
Conversion Time:  
12-bit cycle  
50 nS  
HAC  
t
C
6 μS  
4 μS  
-
-
8 μS  
6 μS  
8-bit cycle  
DATEL  
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA  
Tel: (508) 339-3000  
www.datel.com  
e-mail: help@datel.com  
20 Jan 2012 MDA_ADC-674.A02_D3 Page 6 of 7  

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