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ADC-207MM-QL-C

更新时间： 2024-01-31 09:53:08
品牌 Logo 应用领域
村田 - MURATA /
页数 文件大小 规格书
6页 230K
描述
ADC, Flash Method,

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ADC-207MM-QL-C 技术参数

生命周期：Transferred包装说明：DIP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.63最大模拟输入电压：5 V
最小模拟输入电压：最长转换时间：0.05 µs
转换器类型：ADC, FLASH METHODJESD-30 代码：R-CDIP-T18
长度：24.38 mm最大线性误差 (EL)：0.7812%
模拟输入通道数量：1位数：7
功能数量：1端子数量：18
最高工作温度：125 °C最低工作温度：-55 °C
输出位码：BINARY封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE采样速率：20 MHz
座面最大高度：6.62 mm标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

ADC-207MM-QL-C 数据手册

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®
®
ADC-207  
7-Bit, 20MHz, CMOS Flash A/D Converters  
Æ2  
Æ1  
Æ2  
Æ1  
Æ2  
Æ1  
OUTPUT CODING  
AUTO  
ZERO  
SAMPLE  
N
AUTO  
ZERO  
SAMPLE  
N + 1  
AUTO  
ZERO  
SAMPLE  
N + 2  
(+REFERENCE = +5.12V, –REFERENCE = ground, MIDPOINT = no connection)  
NOTE: The reference should be held to 0.1% accuracy or better. Do not use the +5V  
power supply as a reference input without precision regulation and high frequency  
decoupling.  
Values shown here are for a +5.12V reference. Scale other references proportionally.  
Calibration equipment should test for code changes at the midpoints between these  
center values shown in Table 1. For example, at the half-scale major carry, set the  
input to 2.54V and adjust the reference until the code flickers equally between 63  
and 64. Note also that the weighting for the comparator resistor network leaves the  
first and last thresholds within 1/2LSB of the end points to adjust the code transition  
to the proper midpoint values.  
CLOCK  
OUTPUT  
DATA  
N DATA  
N+1 DATA  
17ns max.  
17ns max.  
TIMING DIAGRAM  
Table 1. ADC-207 Output Coding  
1
MSB  
0
2
3
4
5
6
7
LSB  
0
Analog Input  
(Center Value)  
Hexadecimal  
(Incl. 0V)  
Code  
Overflow  
Decimal  
0.00V  
+0.04V  
+1.28V  
+2.52V  
+2.56V  
+2.60V  
+3.84V  
+5.08V  
+5.12V  
Zero  
+1LSB  
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
1
00  
01  
20  
3F  
40  
41  
60  
7F  
FF  
0
1
+1/4FS  
0
0
32  
+1/2FS – 1LSB  
+1/2FS  
0
1
63  
1
0
64  
+1/2FS + 1LSB  
+3/4FS  
1
1
65  
1
0
96  
+FS  
1
1
127  
255*  
Overflow  
1
1
*Note that the overflow code does not clear the data bits.  
ADC-207 OPERATION  
The ADC-207 uses a switched capacitor scheme in which there is an auto-  
zero phase and a sampling phase. See Figure 1 and Timing Diagram. The  
ADC-207 uses a single clock input. When the clock is at a high state (logic  
1), the ADC-207 is in the auto-zero phase (Ø1). When the clock is at a low  
state (logic 0), the ADC-207 is in the sampling phase (Ø2). During phase  
1, the 128 comparator outputs are shorted to their inputs through CMOS  
switches. This serves the purpose of bringing the inputs and outputs to the  
transition levels of the respective comparators. The inputs to the compara-  
tors are also connected to 128 sampling capacitors. The other end of the  
128 capacitors are also shorted to 128 taps of a resistor ladder, via CMOS  
switches. Therefore, during phase 1 the sampling capacitors are charged to  
the differential voltage between a resistor tap and its respective comparator  
transition voltage.  
two enable lines, CS1 and CS2. Table 2 shows the truth table for chip select  
signals. CS1 has the function of enabling/disabling bits 1 through 7. CS2  
has the function of enabling/disabling bits 1 through 7 and the overflow bit.  
Also, a full-scale input produces all ones, including the overflow bit at the  
output. The ADC-207 has an adjustable resistor ladder string. The top end,  
idle point, and bottom end are brought out for use with applications circuits.  
These pins are called +REFERENCE, MIDPOINT and –REFERENCE,  
respectively. In typical operation +REFERENCE is tied to +5V, –REFERENCE  
is tied to ground, and MIDPOINT is bypassed to ground. Such a configura-  
tion results in a 0 to +5V input voltage range. The MIDPOINT pin can also  
be tied to a +2.5V source to further improve integral linearity. This is usually  
not necessary unless better than 7-bit linearity is needed.  
This eliminates offset differences between comparators and yields better  
temperature performance. During phase 2 (Ø2) the input voltage is applied to  
the 128 capacitors, via CMOS switches. This forces the comparators to trip  
either high or low. Since the comparators during phase 1 were sitting at their  
transition point, they can trip very quickly to the correct state. Also during  
phase 2, the outputs of the comparators are loaded into internal latches  
which in turn feed a128-to-7 encoder. When going back into phase 1, the  
output of the encoder is loaded into an output latch. This latch then feeds the  
3-state output buffer.  
This means that the ADC-207 is of pipeline design. To do a single con-  
version, the ADC-207 requires a positive pulse followed by a negative pulse  
followed by a positive pulse. Continuous conversion requires one cycle/  
sample (one positive pulse and one negative pulse). The 3-state buffer has  
Table 2. Chip Select Truth Table  
CS1  
0
CS2  
0
Bits 1-7  
Overflow Bit  
3-State Mode  
3-State Mode  
Data Outputed  
Data Outputed  
3-State Mode  
3-State Mode  
Data Outputed  
3-State Mode  
1
0
0
1
1
1
NOTE: Reduce the sample time (sample pulse) to 12ns to improve performance  
above 20MHz. Such a configuration will closely resemble an ideal sampler.  
DATEL  
•
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA  
•
Tel: (508) 339-3000  
•
www.datel.com  
•
e-mail: help@datel.com  
MDA_ADC-207.B06 Page 3 of 6  
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