Datasheet > ADAU7112

ADAU7112

更新时间： 2023-12-20 18:45:47

品牌	Logo	应用领域
亚德诺 - ADI		光电二极管转换器
页数	文件大小	规格书
14页	331K
描述
立体声 PDM 至 I2S/TDM 转换器

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数据手册

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ADAU7112 数据手册

Data Sheet

ADAU7112

SPECIFICATIONS

DVDD = 1.10 V to 1.98 V, IOVDD = 1.70 V to 3.63 V, T_A= 25°C, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL INPUT

Input Voltage

High Level (V_IH)

0.7 ×

IOVDD

Low Level (V_IL)

0.3 ×

IOVDD

Input Leakage

High Level (I_IH)

Low Level (I_IL) at 0 V

Input Capacitance (C_I)

DIGITAL OUTPUT

Output Voltage

Digital input pins with pull-down resistor

Guaranteed by design

2.5

μA

High Level (V_OH)

0.85 ×

IOVDD

Source current when output is high (I_OH) = 1 mA

Source current when output is low (I_OL) = 1 mA

Low Level (V_OL)

0.1 ×

IOVDD

Digital Output Pins,

Output Drive

The digital output pins are driving low impedance

printed circuit board (PCB) traces to a high

impedance digital input buffer

IOVDD = 1.8 V Nominal

Drive Strength

IOVDD = 3.3 V Nominal

Drive Strength

2.8

PERFORMANCE

Dynamic Range

126

64×

20 Hz to 20 kHz, −60 dB input, A-weighted filter

(rms), relative to 0 dBFS output

A-weighted filter, fifth-order input, relative to

0 dBFS output

Only 64× is supported

DC to 0.45 × output sampling rate

Signal-to-Noise Ratio

(SNR)

Decimation Ratio

Frequency Response

Stop Band

−0.1

+0.01

0.566 × output

sampling rate

(f_S)

Stop Band Attenuation

Group Delay

Gain

Start-Up Time

Bit Resolution

4.47

FSYNC cycles 0.02 f_Sinput signal

dB PDM to PCM

FSYNC cycles After power-up reset and initialization code is run

Bits

Degrees

Internal and output

Interchannel Phase

CLOCKING

Output Sampling Rate (f_S)

kHz

FSYNC pulse rate

Bit Clock Frequency (f_BCLK

PDM_CLK Frequency

(f_{PDM_CLK}

POWER

)

0.256

12.288

3.072

24.576

6.144

MHz

)

Supply Voltage

Digital Core Voltage

(DVDD Pin)

Input/Output (I/O)

Supply Voltage

(IOVDD Pin)

1.10

1.70

1.98

3.63

Supply for digital circuitry

Supply for I/O circuitry, including pads and level

shifters

Rev. 0 | Page 3 of 14

1 234 5 6 7...14

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