Datasheet > ADAU1788

ADAU1788

更新时间： 2023-12-20 18:45:05

品牌	Logo	应用领域
亚德诺 - ADI		编解码器
页数	文件大小	规格书
226页	2973K
描述
具有音频 DSP 的双 ADC 单 DAC 低功耗编解码器

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ADAU1788 数据手册

Data Sheet

ADAU1788

SPECIFICATIONS

Master clock input = 24.576 MHz, serial input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits,

ambient temperature (T_A) = 25°C, and line output load = 10 kΩ, unless otherwise noted.

ANALOG PERFORMANCE SPECIFICATIONS

Supply voltages AVDD = IOVDD = 1.8 V and DVDD = 0.9 V, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ANALOG-TO-DIGITAL CONVERTERS (ADCs)

ADC Resolution

Digital Gain Step

All ADCs

0.375

Bits

Digital Gain Range

−71

+24

INPUT RESISTANCE

Single-Ended Line Input

Programmable Gain Amplifier (PGA)

Inputs

14.3

20.26

kΩ

0 dB gain

32 dB gain

0.97

kΩ

SINGLE-ENDED LINE INPUT

Full-Scale Input Voltage

PGAx_EN = 0, PGAx_BOOST = 0,

PGAx_SLEW_DIS = 1

0 dBFS

0.49

1.38

V rms

V p-p

0 dBFS

Dynamic Range¹

20 Hz to 20 kHz, −60 dB input

With A-Weighted Filter (RMS)

With Flat 20 Hz to 20 kHz Filter

Signal-to-Noise Ratio (SNR)²

With A-Weighted Filter (RMS)

With Flat 20 Hz to 20 kHz Filter

Interchannel Gain Mismatch

mdB

Total Harmonic Distortion + Noise

(THD + N) Level

20 Hz to 20 kHz, −1 dB full-scale output

−90

0.1

0.2

dBFS

Offset Error

Gain Error

Interchannel Isolation

Power Supply Rejection Ratio (PSRR)

CM capacitor = 10 μF

100 mV p-p at 1 kHz

100 mV p-p at 10 kHz

PGAx_EN = 1, PGA_x_BOOST = 0

100

SINGLE-ENDED PGA INPUT

Full-Scale Input Voltage

0.49

1.38

V rms

V p-p

0 dBFS

Dynamic Range¹

20 Hz to 20 kHz, −60 dB input

With A-Weighted Filter (RMS)

With Flat 20 Hz to 20 kHz Filter

THD + N Level

−88

dBFS

20 Hz to 20 kHz, −1 dBFS output

SNR²

With A-Weighted Filter (RMS)

With Flat 20 Hz to 20 kHz Filter

PGA Gain Variation

Standard deviation

With 0 dB Setting

With 35.25 dB Setting

0.05

0.15

Rev. 0 | Page 7 of 226

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