Data Sheet
ADAU1463/ADAU1467
SPECIFICATIONS
AVDD = 3.3 V 10%, DVDD = 1.2 V 5%, PVDD = 3.3 V 10%, IOVDD = 1.8 V − 5% to 3.3 V + 10%, TA = 25°C, master clock input =
12.288 MHz, core clock (fCORE) = 294.912 MHz, I/O pins set to low drive setting, unless otherwise noted.
Table 2.
Parameter
Min Typ Max
Unit Test Conditions/Comments
POWER
Supply Voltage
Analog Voltage (AVDD)
Digital Voltage (DVDD)
2.97 3.3
1.14 1.2
3.63
1.26
V
V
Supply for analog circuitry, including auxiliary ADCs
Supply for digital circuitry, including the DSP core, ASRCs, and signal
routing
PLL Voltage (PVDD)
I/O Supply Voltage (IOVDD)
Supply Current
2.97 3.3
1.71 3.3
3.63
3.63
V
V
Supply for PLL circuitry
Supply for input/output circuitry, including pads and level shifters
Analog Current (AVDD)
Idle State
Reset State
1.36 1.66
1.00 1.10 40
1.00 1.10 40
2
mA
µA
µA
mA
µA
µA
Power applied, chip not programmed
RESET
held low
Power applied,
PLL Current (PVDD)
Idle State
Reset State
8.3
10.1 12.9
12.288 MHz MCLK with default PLL settings
Power applied, PLL not configured
18.3 18.7 40
18.3 18.7 40
RESET
held low
Power applied,
I/O Current (IOVDD)
Dependent on the number of active serial ports, clock pins, and
characteristics of external loads
Operation State
53
22
4.1
mA
mA
mA
IOVDD = 3.3 V; all serial ports are clock masters
IOVDD = 1.8 V; all serial ports are clock masters
IOVDD = 1.8 V − 5% to 3.3 V + 10%
Power-Down State
Digital Current (DVDD)
ADAU1467 Operation State
Maximum Program
4.2
233
220
495
mA
mA
Typical Program
Test program includes 16-channel I/O, 10-band equalizer (EQ) per channel,
all ASRCs active
Minimal Program
ADAU1463 Operation State
fCORE = 294.912 MHz
Maximum Program
Typical Program
213
mA
Test program includes 2-channel I/O, 10-band EQ per channel
233
220
495
420
mA
mA
Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs
active
Test program includes 2-channel I/O, 10-band EQ per channel
Minimal Program
fCORE = 147.456 MHz
Maximum Program
Typical Program
Minimal Program
Idle State
213
mA
270
110
90
mA
mA
mA
mA
mA
Test program includes 16-channel I/O, 10-band EQ per channel
Test program includes 2-channel I/O, 10-band EQ per channel
Power applied, DSP not enabled
18.3 18.7 19.9
18.3 18.7 19.9
Reset State
RESET
held low
Power applied,
ASYNCHRONOUS SAMPLE RATE
CONVERTERS
Dynamic Range
139
dB
A weighted, 20 Hz to 20 kHz
I/O Sample Rate
6
192
kHz
I/O Sample Rate Ratio
Total Harmonic Distortion Plus Noise
(THD + N)
1:8
7.75:1
−120
dB
CRYSTAL OSCILLATOR
Transconductance
REGULATOR
8.3
10.6 13.4
mS
V
DVDD Voltage
1.14 1.2
Regulator maintains typical output voltage up to a maximum 800 mA load;
IOVDD = 1.8 V − 5% to 3.3 V + 10%
Rev. A | Page 5 of 207
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