Datasheet > ADAQ7767-1

ADAQ7767-1

更新时间： 2024-03-03 10:08:34

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
95页	2724K
描述
Flexible Resistive Input, 24-Bit, 1MSPS, Alias-Free μModule? DAQ Solution

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ADAQ7767-1 数据手册

Preliminary Data Sheet

ADAQ7767-1

Flexible Resistive Input, 24-Bit, 1MSPS, Alias-Free μModule DAQ Solution

► Integrated LDO

FEATURES

► Built-in supply decoupling capacitors

► Configuration through pin strapping or SPI interface

► Digital interface optimized for isolated applications

► Suite of diagnostic check mechanisms

► Operating temperature range: −40°C to +105°C

► Packaging: 12 mm × 6 mm × 1.6 mm 84-ball BGA with 0.8mm

ball-pitch

► 8x footprint reduction versus discrete solution

► Highly integrated data acquisition solution

► Wide Input Common Mode Range of -16V to +12V

► Maximum input range of ±28V differential

► 3 Pin-Selectable Gain Options

► G = 1, 0.364, 0.143 V/V

► 4^thorder AAF with maximum flatness and linear phase

► Full aliasing protection with 80 dB typ rejection

► Excellent device to device phase matching and drift

► Combined precision ac and dc performance

► Total system dynamic range up to 124 dB

► -115 dB typical THD at ±28V input range (IN3)

► 79 dB DC CMRR at ±28V input range (IN3)

► ±3 ppm typ INL

APPLICATIONS

► Universal input measurement platform

► Electrical Test & Measurement

► Sound & Vibration, Acoustic & Material Science R&D

► Control & Hardware in Loop Verification

► Condition monitoring for predictive maintenance

► Audio Test

► 5 ppm/°C max gain drift

► ± 0.2° maximum device phase matching at 20 kHz

► Programmable output data rate, filter type, and latency

► Linear phase digital filter options:

Protected by U.S. Patent 10,680,633 B1

Protected by U.S. Patent 10,979,062 B2

► Wideband low ripple FIR filter (256 kSPS, 110 kHz max

input BW)

► Sinc5 Filter (1.024 MSPS, 208.9 kHz max input BW, 4 uS

max group delay)

► Sinc3 Filter (50/60Hz rejection)

FUNCTIONAL BLOCK DIAGRAM

11Ω

1uF

VDD_IO = 1.7V to 3.6V

1uF

2.2uF

Example 1

Example 2

Example 3

ADR4540

1uF 1uF

1uF

IN_LDO =

5.1V to 5.5V

IN3+

+24V

SYNC_IN

SYNC_OUT

RESET

IN_LDO

ADAQ7767-1

LDO

DRDY

EN_LDO

1uF

DIGITAL

INTERFACE

AND LOGIC

+12V

ADC POWER MANAGEMENT

CONFIGURABLE

IN3+

IN2+

IN1+

SCLK

DOUT/RDY

SDI

4^thOrder

LPF

IN3+

24-BIT

∑-Δ

ADC

DRIVER

WIDEBAND

FIR

PIN/SPI

IN3-

IN1−

IN2−

IN3−

SINC5

1.024 MSPS

CLOCK

MANAGEMENT

SINC3

50Hz/60Hz

VCM_FDA

-14V

CLOCK

SOURCE

-28V

CMOS, XTAL, OR LVDS

Figure 1. Block Diagram

Rev. PrE

Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to

change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

DOCUMENT FEEDBACK

TECHNICAL SUPPORT

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