Datasheet > ADAQ7769-1

ADAQ7769-1

更新时间： 2024-09-25 17:02:03

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
115页	1248K
描述
High Input Impedance, Programmable Gain, 24-Bit, 1MSPS, Alias-Free μModule? DAQ Solution

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ADAQ7769-1 数据手册

Preliminary Data Sheet

ADAQ7769-1

High Input Impedance, Programmable Gain, 24-Bit, 1MSPS, Alias-Free μModule

DAQ Solution

► Integrated LDO

FEATURES

► Built-in supply decoupling capacitors

► Configuration through pin strapping or SPI interface

► Digital interface optimized for isolated applications

► Suite of diagnostic check mechanisms

► Operating temperature range: −40°C to +105°C

► Packaging: 12.00 mm × 6.00 mm 84-ball CSP_BGA with an 0.80

mm ball pitch

► 11x footprint reduction versus discrete solution

► Highly integrated data acquisition solution

► Wide Input Common Mode Range

► Maximum unipolar input range of +24V or −22V

► 8 Programmable Binary Gain Options from 1 to 128 V/V

► 3 Pin-Selectable AAF Gain Options

► G = 1, 0.364, 0.143 V/V

► 4^thorder AAF with maximum flatness and linear phase

► Full aliasing protection with 80 dB typical rejection

► Excellent device-to-device phase matching and drift

► Combined precision ac and dc performance

► Total system dynamic range up to 130 dB

► -110 dB typical THD at 1kHz input tone, Total Gain = 1

► 81 dB typical DC CMRR at Total Gain = 1

► 5 pA typical input bias current at 25°C

APPLICATIONS

► Universal input measurement platform

► Electrical Test & Measurement

► Sound & Vibration, Acoustic & Material Science R&D

► Control & Hardware in Loop Verification

► Condition monitoring for predictive maintenance

► Audio Test

► ±TBD ppm typical INL

► 5 ppm/°C max gain drift

► ± 0.2° maximum device-to-device phase mismatch at 20 kHz

► Programmable output data rate, filter type, and latency

► Linear phase digital filter options:

Protected by U.S. Patent 10,680,633 B1 and 10,979,062 B2.

► Wideband low ripple FIR filter (256 kSPS, 110 kHz max

input BW)

► Sinc5 Filter (1.024 MSPS, 208.9 kHz max input BW, 4 uS

max group delay)

► Sinc3 Filter (50/60Hz rejection)

FUNCTIONAL BLOCK DIAGRAM

IN_LDO =

5.1V to 5.5V

11Ω

1μF

VDD_IO = 1.7V to 3.6V

1μF

2.2μF

ADR4540

1μF 1μF

1μF

VDD_PGA = +27V VDD_PGA = +15V

VDD_PGA = +5V

1μF

VSS_PGA = −3V

VSS_PGA = −15V VSS_PGA = −25V

IN+

+24V

SYNC_IN

SYNC_OUT

RESET

ADAQ7769-1

IN+

LDO

+12.5V

VDD_PGA

DRDY

VDD_PGA

EN_PGA

DIGITAL

INTERFACE

AND LOGIC

+12V

ADC POWER MANAGEMENT

CONFIGURABLE

1μF

SCLK

DOUT/RDY

SDI

4^thOrder

LPF

IN+

24-BIT

∑-Δ

ADC

DRIVER

WIDEBAND

FIR

PIN/SPI

IN-

IN+

IN-

PGA

SINC5

1.024 MSPS

CLOCK

MANAGEMENT

SINC3

50Hz/60Hz

VCM_FDA

-11V

-22V

-12.5V

*AAF Input ABS MAX ratings:

When using IN1_AAF or IN2_AAF

limit PGA supplies to ±15V to AGND.

CLOCK

SOURCE

1μF

VSS_PGA

CMOS, XTAL, OR LVDS

When using IN3_AAF,

limit PGA supplies to ±36V to AGND.

Figure 1. Block Diagram

Rev. PrC

Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to

change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

DOCUMENT FEEDBACK

TECHNICAL SUPPORT

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ADAQ7988	ADI	获取价格	16-Bit, 1 MSPS, Integrated Data Acquisition Subsystem
ADAQ7988BCCZ	ADI	获取价格	16-Bit, 1 MSPS, Integrated Data Acquisition Subsystem
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