Datasheet > ADA4558WHCPZ-RL

ADA4558WHCPZ-RL

更新时间： 2022-06-24 15:43:28

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
12页	385K
描述
Bridge Sensor Signal Conditioner IC with LIN Interface, Nonlinearity Correction, Temperature Compensation

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ADA4558WHCPZ-RL 数据手册

Data Sheet

ADA4558

PCB LAYOUT GUIDELINES

Figure 5. Example PCB Layout

The following items outline best practice for PCB layout.

•

Shield the VDD12 line from VPOS, VNEG, and VREG

using a ground plane.

Connect DGND and LINGND to AGND at a single point.

Use a short narrow trace for DGND and a wide trace for

LINGND.

TESTD is connected internally to DGND. Connect Pin 3 to

a small DGND plane to avoid multiple connections

between AGND and DGND.

To minimize total ground plane impedance, use a separate

ground layer, if available, with many via connections to the

top layer ground plane.

•

Place the 220 pF CLIN capacitor close to the IC between

the LIN and LINGND traces.

•

Place the CREG, CIN, and C1_8V capacitors close to the

IC using short, thick tracks. These components decouple

the supplies and reduce high frequency noise on these nodes.

The length of the C1_8V traces is critical. Keep the traces

as short as possible.

Shield the noisy DVDD regulator pin from the sensitive

analog circuitry at VPOS, VNEG, and VREG.

Maintain shielded matched differential lines for VNEG and

VPOS to ensure that noise pickup is both minimal and

common mode. The PGA can potentially obtain significant

noise at this point.

•

When a second routing layer is available, the LINGND

trace can be connected to the AGND plane with a large via

close to CDVDD. Connect DGND to AGND at this point

with a narrow trace.

•

Shield the VPOS trace from the VREG trace because

VREG can have noise pickup during EMC testing.

Rev. 0 | Page 11 of 12

1...8 9 101112

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