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ADA4411-3ARQZ-RL PDF预览

ADA4411-3ARQZ-RL

更新时间: 2024-01-04 13:47:44
品牌 Logo 应用领域
亚德诺 - ADI 消费电路商用集成电路光电二极管
页数 文件大小 规格书
16页 395K
描述
Integrated Triple Video Filter and Buffer with Selectable Cutoff Frequencies and Multiplexed Inputs for RGB, HD/SD

ADA4411-3ARQZ-RL 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP, SSOP24,.24针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.09
Is Samacsys:N其他特性:IT CAN ALSO OPERATE WITH 4.5V TO 12V SINGLE SUPPLY
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:R-PDSO-G24
JESD-609代码:e3长度:8.6614 mm
湿度敏感等级:1功能数量:1
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP24,.24
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:+-5 V
认证状态:Not Qualified座面最大高度:1.7526 mm
子类别:Other Consumer ICs最大压摆率:60 mA
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2.25 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9116 mm
Base Number Matches:1

ADA4411-3ARQZ-RL 数据手册

 浏览型号ADA4411-3ARQZ-RL的Datasheet PDF文件第8页浏览型号ADA4411-3ARQZ-RL的Datasheet PDF文件第9页浏览型号ADA4411-3ARQZ-RL的Datasheet PDF文件第10页浏览型号ADA4411-3ARQZ-RL的Datasheet PDF文件第12页浏览型号ADA4411-3ARQZ-RL的Datasheet PDF文件第13页浏览型号ADA4411-3ARQZ-RL的Datasheet PDF文件第14页 
ADA4411-3  
APPLICATIONS  
OVERVIEW  
CUTOFF FREQUENCY SELECTION  
With its high impedance multiplexed inputs and high output  
drive, the ADA4411-3 is ideally suited to video reconstruction  
and antialias filtering applications. The high impedance inputs  
give designers flexibility with regard to how the input signals  
are terminated. Devices with DAC current source outputs that  
feed the ADA4411-3 can be loaded in whatever resistance  
provides the best performance, and devices with voltage outputs  
can be optimally terminated as well. The ADA4411-3 outputs  
can each drive up to two source-terminated 75 Ω loads and can  
therefore directly drive the outputs from set-top boxes, DVD  
players, and the like without the need for a separate output  
buffer.  
Four combinations of cutoff frequencies are provided for the  
video signals. The cutoff frequencies have been selected to  
correspond with the most commonly deployed component  
video scanning systems. Selection between the cutoff frequency  
combinations is controlled by the logic signals applied to the  
F_SEL_A and F_SEL_B inputs. Table 7 summarizes cutoff  
frequency selection.  
Table 7. Filter Cutoff Frequency Selection  
F_SEL_A F_SEL_B Y/G Cutoff Pb/B Cutoff Pr/R Cutoff  
0
0
1
1
0
1
0
1
36 MHz  
36 MHz  
18 MHz  
9 MHz  
36 MHz  
18 MHz  
18 MHz  
9 MHz  
36 MHz  
18 MHz  
18 MHz  
9 MHz  
Binary control inputs are provided to select cutoff frequency,  
throughput gain, and input signal. These inputs are compatible  
with 3 V and 5 V TTL and CMOS logic levels referenced to  
GND. The disable feature is asserted by pulling the DISABLE  
pin to the positive supply.  
OUTPUT DC OFFSET CONTROL  
The LEVEL1 and LEVEL2 inputs work as a differential, input-  
referred output offset control. In other words, the output offset  
voltage of a given channel is equal to the difference in voltage  
between the LEVEL1 and LEVEL2 inputs, multiplied by the  
overall filter gain. This relationship is expressed in Equation 1.  
The LEVEL1 and LEVEL2 inputs comprise a differential input  
that controls the dc level at the output pins.  
MULTIPLEXER SELECT INPUTS  
VOS (OUT) = (LEVEL1LEVEL2)(G)  
(1)  
Selection between the two multiplexer inputs is controlled by  
the logic signals applied to the MUX inputs. Table 6  
summarizes the multiplexer operation.  
LEVEL1 and LEVEL2 are the voltages applied to the respective  
inputs, and G is the throughput gain.  
For example, with the G_SEL input set for ×2 gain, setting  
LEVEL1 to 3ꢀꢀ mV and LEVEL2 to ꢀ V shifts the offset voltages  
at the ADA4411-3 outputs to 6ꢀꢀ mV. This particular setting  
can be used in most single-supply applications to keep the  
output swings safely above the negative supply rail.  
THROUGHPUT GAIN  
The throughput gain of the ADA4411-3 signal paths can  
be either × 2 or × 4. Gain selection is controlled by the logic  
signal applied to the G_SEL pin. Table 6 summarizes how the  
gain is selected.  
The maximum differential voltage that can be applied across the  
LEVEL1 and LEVEL2 inputs is 5ꢀꢀ mV. From a single-ended  
standpoint, the LEVEL1 and LEVEL2 inputs have the same  
range as the filter inputs. See the Specifications tables for the  
limits. The LEVEL1 and LEVEL2 inputs must each be bypassed  
to GND with a ꢀ.1 μF ceramic capacitor.  
DISABLE  
The ADA4411-3 includes a disable feature that can be used  
to save power when a particular device is not in use. As  
indicated in the Overview section, the disable feature is  
asserted by pulling the DISABLE pin to the positive supply.  
Table 6 summarizes the disable feature operation. The  
DISABLE pin also functions as a reference level for the logic  
inputs and therefore must be connected to ground when the  
device is not disabled.  
In single-supply applications, a positive output offset must be  
applied to keep the negative-most excursions of the output  
signals above the specified minimum output swing limit.  
Table 6. Logic Pin Function Description  
DISABLE  
MUX  
G_SEL  
VS+ = Disabled  
GND = Enabled  
1 = Channel 1 Selected  
0 = Channel 2 Selected  
1 = ×2 Gain  
0 = ×4 Gain  
Rev. 0 | Page 11 of 16  
 
 
 
 

ADA4411-3ARQZ-RL 替代型号

型号 品牌 替代类型 描述 数据表
ADA4411-3ARQZ ADI

完全替代

Integrated Triple Video Filter and Buffer with Selectable Cutoff Frequencies and Multiplex
ADA4411-3ARQZ-R7 ADI

完全替代

Integrated Triple Video Filter and Buffer with Selectable Cutoff Frequencies and Multiplex

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