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AD9953YSVZ

更新时间： 2024-01-02 08:02:25
品牌 Logo 应用领域
亚德诺 - ADI DSP外围设备微控制器和处理器外围集成电路PC时钟
页数 文件大小 规格书
32页 574K
描述
400 MSPS, 14-Bit, 1.8 V CMOS Direct Digital Synthesizer

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AD9953YSVZ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：TFQFP,针数：48
Reach Compliance Code：unknown风险等级：5.17
边界扫描：NO最大时钟频率：400 MHz
JESD-30 代码：S-PQFP-G48JESD-609代码：e3
长度：7 mm低功率模式：YES
湿度敏感等级：3端子数量：48
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260认证状态：COMMERCIAL
座面最大高度：1.2 mm最大供电电压：1.89 V
最小供电电压：1.71 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：7 mmuPs/uCs/外围集成电路类型：DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATOR
Base Number Matches：1

AD9953YSVZ 数据手册

 浏览型号AD9953YSVZ的Datasheet PDF文件第5页浏览型号AD9953YSVZ的Datasheet PDF文件第6页浏览型号AD9953YSVZ的Datasheet PDF文件第7页浏览型号AD9953YSVZ的Datasheet PDF文件第9页浏览型号AD9953YSVZ的Datasheet PDF文件第10页浏览型号AD9953YSVZ的Datasheet PDF文件第11页 
AD9953  
PIN FUNCTION DESCRIPTIONS  
Table 3. 48-Lead TQFP/EP  
Pin No.  
Mnemonic  
I/O Description  
1
I/O UPDATE  
I
The rising edge transfers the contents of the internal buffer memory to the I/O registers. This pin  
must be set up and held around the SYNC_CLK output signal.  
2, 34  
3, 33, 42  
4, 6, 13,  
DVDD  
DGND  
AVDD  
I
I
I
Digital Power Supply Pins (1.8 V).  
Digital Power Ground Pins.  
Analog Power Supply Pins (1.8 V).  
16, 18, 19,  
25, 27, 29  
5, 7, 14,  
15, 17, 22,  
26, 32  
AGND  
I
Analog Power Ground Pins.  
8
OSC/REFCLK  
OSC/REFCLK  
I
I
Complementary Reference Clock/Oscillator Input. When the REFCLK port is operated in single-  
ended mode, REFCLK should be decoupled to AVDD with a 0.1 μF capacitor.  
9
Reference Clock/Oscillator Input. See Clock Input section for details on the OSCILLATOR/REFCLK  
operation.  
10  
11  
CRYSTAL OUT  
CLKMODESELECT  
O
I
Output of the Oscillator Section.  
Control Pin for the Oscillator Section. When high, the oscillator section is enabled. When low, the  
oscillator section is bypassed.  
12  
LOOP_FILTER  
I
This pin provides the connection for the external zero compensation network of the REFCLK  
multiplier’s PLL loop filter. The network consists of a 1 kΩ resistor in series with a 0.1 μF capacitor  
tied to AVDD.  
20  
21  
23  
24  
IOUT  
O
O
I
Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND.  
DAC Output. Should be biased through a resistor to AVDD, not AGND.  
DAC Biasline Decoupling Pin. A 0.1 ꢀF capacitor to AGND is recommended.  
A resistor (3.92 kΩ nominal) connected from AGND to DAC_RSET establishes the reference current  
for the DAC.  
IOUT  
DACBP  
DAC_RSET  
I
35  
36  
PWRDWNCTL  
RESET  
I
I
Input Pin Used as an External Power-Down Control (see Table 10 for details).  
Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9953 to the initial state,  
as described in the I/O port register map.  
37  
38  
IOSYNC  
SDO  
I
Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O  
operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC is  
returned low. If unused, ground this pin; do not allow this pin to float.  
When operating the I/O port as a 3-wire serial port, this pin serves as the serial data output. When  
operated as a 2-wire serial port, this pin is unused and can be left unconnected.  
O
39  
40  
41  
CS  
I
I
This pin functions as an active low chip select that allows multiple devices to share the I/O bus.  
This pin functions as the serial data clock for I/O operations.  
SCLK  
SDIO  
I/O When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input only.  
When operated as a 2-wire serial port, this pin is the bidirectional serial data pin.  
43  
44  
DVDD_I/O  
SYNC_IN  
I
I
Digital Power Supply (for I/O Cells Only, 3.3 V).  
Input Signal Used to Synchronize Multiple AD9953s. This input is connected to the SYNC_CLK  
output of a master AD9953.  
45  
46  
SYNC_CLK  
OSK  
O
I
Clock Output Pin that Serves as a Synchronizer for External Hardware.  
Input Pin Used to Control the Direction of the Shaped On-Off Keying Function when Programmed  
for Operation. OSK is synchronous to the SYNC_CLK pin. When OSK is not programmed, this pin  
should be tied to DGND.  
47, 48  
<49>  
PS0, PS1  
AGND  
I
I
Input pin used to select one of the four internal profiles. Profile <1:0> are synchronous to the  
SYNC_CLK pin. Any change in these inputs transfers the contents of the internal buffer memory  
to the I/O registers (sends an internal I/O UPDATE).  
The exposed paddle on the bottom of the package is a ground connection for the DAC and must  
be attached to AGND in any board layout.  
Rev. A | Page 8 of 32  
 
1...567891011...32

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