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AD9956YCPZ

更新时间: 2024-11-11 20:10:43
品牌 Logo 应用领域
亚德诺 - ADI 数据分配系统
页数 文件大小 规格书
34页 482K
描述
400 MSPS 14-Bit DAC 48-Bit FTW 1.8 V CMOS DDS Based AgileRF™ Synthesizer

AD9956YCPZ 数据手册

 浏览型号AD9956YCPZ的Datasheet PDF文件第2页浏览型号AD9956YCPZ的Datasheet PDF文件第3页浏览型号AD9956YCPZ的Datasheet PDF文件第4页浏览型号AD9956YCPZ的Datasheet PDF文件第5页浏览型号AD9956YCPZ的Datasheet PDF文件第6页浏览型号AD9956YCPZ的Datasheet PDF文件第7页 
2.7 GHz DDS-Based AgileRFTM Synthesizer  
AD9956  
3.3 V supply for I/O and charge pump  
Software controlled power-down  
48-lead LFCSP package  
FEATURES  
400 MSPS internal DDS clock speed  
48-bit frequency tuning word  
14-bit programmable phase offset  
Integrated 14-bit DAC  
Automatic linear frequency sweeping capability (in DDS)  
Programmable charge pump current (up to 4 mA)  
Phase modulation capability  
Excellent dynamic performance  
Multichip synchronization  
Phase noise ≤ 135 dBc/Hz @ 1 KHz offset  
−80 dB SFDR @ 160 MHz ( 100 KHz offset IOUT  
25 Mb/s write-speed serial I/O control  
200 MHz phase frequency detector inputs  
Dual-mode PLL lock detect  
655 MHz CML-mode PECL-compliant driver  
)
APPLICATIONS  
655 MHz programmable input dividers for the phase  
Agile LO frequency synthesis  
frequency detector (÷M, ÷N) {M, N = 1..16} (bypassable)  
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)  
8 phase/frequency profiles  
FM chirp source for radar and scanning systems  
Automotive radars  
Test and measurement equipment  
Acousto-optic device drivers  
1.8 V supply for device operation  
FUNCTIONAL BLOCK DIAGRAM  
DAC_RSET  
DELTA  
DDS CORE  
PHASE TO  
PHASE  
OFFSET  
48  
FREQUENCY  
TUNING WORD  
FREQUENCY  
ACCUMULATOR  
IOUT  
IOUT  
19  
14  
AMPLITUDE  
CONVERSION  
DAC  
PHASE  
ACCUMULATOR  
DELTA  
FREQUENCY  
RAMP RATE  
FTW  
48  
PHASE  
OFFSET  
WORD  
14  
24  
SYSCLK  
SYSCLK  
16  
PLL_LOCK/SYNC_IN  
I/O_UPDATE  
I/O_RESET  
TIMING AND CONTROL LOGIC  
OSCILLATOR  
LOCK  
DETECT  
CHARGE  
PUMP  
SCALER  
SYSCLK  
SYNC_CLK  
SYNC_OUT  
÷4  
RF-DIVIDER  
÷R  
÷M  
÷N  
3
REFCLK  
REFCLK  
BUFFER  
Φ
CHARGE  
PUMP  
CP_OUT  
CML CLOCK DRIVER  
3
BUFFER  
FROM PLLOSC  
DRV DRV DRV_RSET  
RESET I/O PORT  
CP_RSET  
PS<2:0>  
PLLREF/ PLLOSC/  
PLLREF PLLOSC  
Figure 1.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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