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AD9952YSVZ PDF预览

AD9952YSVZ

更新时间： 2024-02-18 15:19:33
品牌 Logo 应用领域
亚德诺 - ADI DSP外围设备微控制器和处理器外围集成电路PC时钟
页数 文件大小 规格书
28页 569K
描述
400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer

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中文翻译

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AD9952YSVZ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：HTFQFP,针数：48
Reach Compliance Code：unknown风险等级：5.72
边界扫描：NO最大时钟频率：400 MHz
JESD-30 代码：S-PQFP-G48JESD-609代码：e3
长度：7 mm低功率模式：NO
湿度敏感等级：3端子数量：48
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HTFQFP
封装形状：SQUARE封装形式：FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260认证状态：COMMERCIAL
座面最大高度：1.2 mm最大供电电压：1.89 V
最小供电电压：1.71 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：7 mmuPs/uCs/外围集成电路类型：DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATOR
Base Number Matches：1

AD9952YSVZ 数据手册

 浏览型号AD9952YSVZ的Datasheet PDF文件第5页浏览型号AD9952YSVZ的Datasheet PDF文件第6页浏览型号AD9952YSVZ的Datasheet PDF文件第7页浏览型号AD9952YSVZ的Datasheet PDF文件第9页浏览型号AD9952YSVZ的Datasheet PDF文件第10页浏览型号AD9952YSVZ的Datasheet PDF文件第11页 
AD9952  
Pin No.  
23  
24  
Mnemonic  
DACBP  
DAC_RSET  
I/O Description  
I
I
DAC Biasline Decoupling Pin. A 0.1 μF capacitor to AGND is recommended.  
A resistor (3.92 kΩ nominal) connected from AGND to DAC_RSET establishes the reference current  
for the DAC.  
28  
30  
31  
35  
36  
COMP_OUT  
COMP_IN  
COMP_IN  
PWRDWNCTL  
RESET  
O
I
I
Comparator Output.  
Comparator Input.  
Comparator Complementary Input.  
I
I
Input Pin Used as an External Power-Down Control. See Table 7 for additional information.  
Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9952 to the initial state,  
as described in the I/O port register map (see Table 5).  
37  
38  
IOSYNC  
SDO  
I
Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O  
operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC is  
returned low. If unused, ground this pin; do not allow this pin to float.  
When operating the I/O port as a 3-wire serial port, this pin serves as the serial data output. When  
operated as a 2-wire serial port, this pin is unused and can be left unconnected.  
O
39  
40  
41  
CS  
I
I
This pin functions as an active low chip select that allows multiple devices to share the I/O bus.  
This pin functions as the serial data clock for I/O operations.  
SCLK  
SDIO  
I/O When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input only.  
When operated as a 2-wire serial port, this pin is the bidirectional serial data pin.  
43  
44  
DVDD_I/O  
SYNC_IN  
I
I
Digital Power Supply. For I/O cells only, 3.3 V.  
Input signal used to synchronize multiple AD9952s. This input is connected to the SYNC_CLK  
output of a master AD9952.  
45  
46  
SYNC_CLK  
OSK  
O
I
Clock output pin that serves as a synchronizer for external hardware.  
Input pin used to control the direction of the shaped on-off keying function when programmed  
for operation. OSK is synchronous to the SYNC_CLK pin. When OSK is not programmed, this pin  
should be tied to DGND.  
Paddle  
Exposed Paddle  
I
The exposed paddle on the bottom of the package is a ground connection for the DAC and must  
be attached to AGND in any board layout. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or  
3.3 V; however, the DVDD pins (Pin 2 and Pin 34) can only be powered to 1.8 V.  
Rev. B | Page 8 of 28  
1...567891011...28

中文翻译

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AD9952YSVZ 替代型号

型号 品牌 替代类型 描述 数据表
AD9952YSV ADI

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 		400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer
AD9952YSV-REEL7 ADI

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 		400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer

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