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AD9915-PCBZ

更新时间： 2024-02-08 14:31:23

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
48页	877K
描述
2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC

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技术参数
数据手册

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AD9915-PCBZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	,
针数：	88	Reach Compliance Code：	compliant
ECCN代码：	3A001.A.13.B	HTS代码：	8542.39.00.01
风险等级：	2.16	Is Samacsys：	N
商用集成电路类型：	TONE/MUSIC SYNTHESIZER	JESD-609代码：	e3
湿度敏感等级：	3	端子面层：	Tin (Sn)
Base Number Matches：	1

AD9915-PCBZ 数据手册

AD9915

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PARALLEL PORT TIMING

Write Timing

Address Setup Time to WR Active

Address Hold Time to WR Inactive

Data Setup Time to WR Inactive

Data Hold Time to WR Inactive

WR Minimum Low Time

3.8

2.1

3.8

10.5

WR Minimum High Time

Minimum WR Time

Read Timing

Address to Data Valid

Address Hold to RD Inactive

RD Active to Data Valid

RD Inactive to Data Tristate

RD Minimum Low Time

RD Minimum High Time

SERIAL PORT TIMING

SCLK Clock Rate (1/t_CLK

)

MHz

SCLK duty cycle = 50%

SCLK Pulse Width High, t_HIGH

SCLK Pulse Width Low, t_LOW

SDIO to SCLK Setup Time, t_DS

SDIO to SCLK Hold Time, t_DH

1.5

5.1

4.9

SCLK Falling Edge to Valid Data on

SDIO/SDO, t_DV

CS to SCLK Setup Time, t_S

CS to SCLK Hold Time, t_H

CS Minimum Pulse Width High, t_PWH

DATA PORT TIMING

D[31:0] Setup Time to SYNC_CLK

D[31:0] Hold Time to SYNC_CLK

F[3:0] Setup Time to SYNC_CLK

F[3:0] Hold Time to SYNC_CLK

IO_UPDATE Pin Setup Time to

SYNC_CLK

IO_UPDATE Pin Hold Time to

SYNC_CLK

Profile Pin Setup Time to SYNC_CLK

Profile Pin Hold Time to SYNC_CLK

DR_CTL/DR_HOLD Setup Time to

SYNC_CLK

DR_CTL/DR_HOLD Hold Time to

SYNC_CLK

DATA LATENCY (PIPELINE DELAY)

Single Tone Mode (Matched Latency

Disabled)

SYSCLK cycles = f_S= system clock frequency

in GHz

Frequency

Phase

Amplitude

320

296

104

SYSCLK cycles

Single Tone Mode (Matched Latency

Enabled)

Frequency

Phase

Amplitude

320

SYSCLK cycles

Rev. A | Page 6 of 48

1...3 4 567 8 9...48

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