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AD9915-PCBZ

更新时间： 2024-01-21 06:17:51

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
48页	877K
描述
2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC

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技术参数
数据手册

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AD9915-PCBZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	,
针数：	88	Reach Compliance Code：	compliant
ECCN代码：	3A001.A.13.B	HTS代码：	8542.39.00.01
风险等级：	2.16	Is Samacsys：	N
商用集成电路类型：	TONE/MUSIC SYNTHESIZER	JESD-609代码：	e3
湿度敏感等级：	3	端子面层：	Tin (Sn)
Base Number Matches：	1

AD9915-PCBZ 数据手册

Data Sheet

AD9915

AC SPECIFICATIONS

AVDD (1.8V) and DVDD (1.8V) = 1.8 V 5%, AVDD3 (3.3V) and DVDD_I/O (3.3V) = 3.3 V 5%, T_A= 25°C, R_SET= 3.3 kΩ, I_OUT

20 mA, external reference clock frequency = 2.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REF CLK INPUT

Input frequency range

REF CLK Multiplier Bypassed

Input Frequency Range

Duty Cycle

500

2500

MHz

Maximum f_OUTis 0.4 × f_SYSCLK

Minimum Differential Input Level

System Clock (SYSCLK) PLL Enabled

VCO Frequency Range

VCO Gain (K_V)

Maximum PFD Rate

CLOCK DRIVERS

632

mV p-p

Equivalent to 316 mV swing on each leg

2400

2500

125

MHz

MHz/V

MHz

SYNC_CLK Output Driver

Frequency Range

Duty Cycle

Rise Time/Fall Time (20% to 80%)

SYNC_OUT Output Driver

Frequency Range

156

MHz

650

10 pF load

6.5

MHz

Duty Cycle

CFR2 register, Bit 9 = 1

10 pF load

Rise Time (20% to 80%)

Fall Time (20% to 80%)

DAC OUTPUT CHARACTERISTICS

Output Frequency Range (1^stNyquist

Zone)

1350

1670

1250

MHz

Output Resistance

Single-ended (each pin internally terminated to

AVDD (3.3V))

Output Capacitance

Full-Scale Output Current

Gain Error

Output Offset

Voltage Compliance Range

20.48

+10

0.6

AVDD +

0.50

% FS

μA

Range depends on DAC R_SETresistor

−10

AVDD −

0.50

Wideband SFDR

See the Typical Performance Characteristics

section

122.5 MHz Output

305.3 MHz Output

497.5 MHz Output

978.2 MHz Output

Narrow-Band SFDR

−67

−66

−59

−60

dBc

0 MHz to 1250 MHz

See the Typical Performance Characteristics

section

122.5 MHz Output

305.3 MHz Output

497.5 MHz Output

−95

−92

dBc

500 kHz

978.2 MHz Output

DIGITAL TIMING SPECIFICATIONS

Time Required to Enter Power-Down

Power-down mode loses DAC/PLL calibration

settings

Time Required to Leave Power-Down

Minimum Master Reset time

250

Must recalibrate DAC/PLL

SYSCLK cycles

µs

Maximum DAC Calibration Time (t_CAL

)

152

f_CAL= f_SYSCLK/384 USR0 register, Bit 6 = 0; see the

DAC Calibration Output section for formula

Maximum PLL Calibration Time (t_{REF_CLK}

)

PFD rate = 25 MHz

PFD rate = 50 MHz

Maximum Profile Toggle Rate

SYNC_CLK period

Rev. A | Page 5 of 48

1 2 3 456 7 8...48

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