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AD9915-PCBZ PDF预览

AD9915-PCBZ

更新时间: 2024-01-06 15:18:35
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
48页 877K
描述
2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC

AD9915-PCBZ 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active包装说明:,
针数:88Reach Compliance Code:compliant
ECCN代码:3A001.A.13.BHTS代码:8542.39.00.01
风险等级:2.16Is Samacsys:N
商用集成电路类型:TONE/MUSIC SYNTHESIZERJESD-609代码:e3
湿度敏感等级:3端子面层:Tin (Sn)
Base Number Matches:1

AD9915-PCBZ 数据手册

 浏览型号AD9915-PCBZ的Datasheet PDF文件第1页浏览型号AD9915-PCBZ的Datasheet PDF文件第2页浏览型号AD9915-PCBZ的Datasheet PDF文件第4页浏览型号AD9915-PCBZ的Datasheet PDF文件第5页浏览型号AD9915-PCBZ的Datasheet PDF文件第6页浏览型号AD9915-PCBZ的Datasheet PDF文件第7页 
Data Sheet  
AD9915  
GENERAL DESCRIPTION  
The AD9915 is a direct digital synthesizer (DDS) featuring a  
12-bit DAC. The AD9915 uses advanced DDS technology,  
coupled with an internal high speed, high performance DAC  
to form a digitally programmable, complete high frequency  
synthesizer capable of generating a frequency-agile analog  
output sinusoidal waveform at up to 1.0 GHz. The AD9915  
enables fast frequency hopping and fine tuning resolution  
(64-bit capable using programmable modulus mode). The  
AD9915 also offers fast phase and amplitude hopping capability.  
The frequency tuning and control words are loaded into the  
AD9915 via a serial or parallel I/O port. The AD9915 also  
supports a user defined linear sweep mode of operation for  
generating linear swept waveforms of frequency, phase, or  
amplitude. A high speed, 32-bit parallel data input port is  
included, enabling high data rates for polar modulation  
schemes and fast reprogramming of the phase, frequency, and  
amplitude tuning words.  
The AD9915 is specified to operate over the extended industrial  
temperature range (see the Absolute Maximum Ratings  
section).  
AD9915  
OUTPUT  
DDS  
SHIFT  
OSK  
DAC_RSET  
KEYING  
AMPLITUDE (A)  
PHASE (θ)  
2
Acos (ωt + θ)  
Asin (ωt + θ)  
A
DRCTL  
DRHOLD  
DIGITAL  
RAMP  
GENERATOR  
AOUT  
AOUT  
DAC  
12-BIT  
DATA  
ROUTE  
θ
FREQUENCY (ω)  
DROVER  
AND  
ω
PARTITION  
CONTROL  
CLOCK  
3
INTERNAL  
PROGRAMMING  
REGISTERS  
PS[2:0]  
SYSCLK  
I/O_UPDATE  
REF_CLK  
REF_CLK  
INTERNAL CLOCK TIMING  
AND CONTROL  
32  
4
PLL  
D0 TO D31  
POWER-  
DOWN  
CONTROL  
F0 TO F3  
MULTICHIP  
SYNCHRONIZATION  
SYNC_CLK  
Figure 2. Detailed Block Diagram  
Rev. A | Page 3 of 48  
 

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