AD9854
PIN FUNCTION DESCRIPTIONS
Pin
No.
Pin Name
Function
1–8
D7–D0
DVDD
Eight-Bit Bidirectional Parallel Programming Data Inputs. Used only in parallel programming mode.
Connections for the Digital Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
and DGND.
9, 10, 23,
24, 25, 73,
74, 79, 80
11, 12, 26, DGND
27, 28, 72,
75, 76, 77,
78
Connections for Digital Circuitry Ground Return. Same potential as AGND.
13, 35, 57, NC
58, 63
No Internal Connection.
14–19
A5–A0
Six-Bit Parallel Address Inputs for Program Registers. Used only in parallel programming mode. A0, A1,
and A2 have a second function when the serial programming mode is selected. See immediately below.
(17)
A2/IO RESET Allows a RESET of the serial communications bus that is unresponsive due to improper program-
ming protocol. Resetting the serial bus in this manner does not affect previous programming nor
does it invoke the “default” programming values seen in the Table V. Active HIGH.
(18)
(19)
20
A1/SDO
A0/SDIO
I/O UD
Unidirectional Serial Data Output for Use in 3-Wire Serial Communication Mode.
Bidirectional Serial Data Input/Output for Use in 2-Wire Serial Communication Mode.
Bidirectional Frequency Update Signal. Direction is selected in control register. If selected as an input,
a rising edge will transfer the contents of the programming registers to the internal works of the IC for
processing. If I/O UD is selected as an output, an output pulse (low to high) of eight system clock cycle
duration indicates that an internal frequency update has occurred.
21
22
29
WRB/SCLK
RDB/CSB
Write Parallel Data to Programming Registers. Shared function with SCLK. Serial clock signal
associated with the serial programming bus. Data is registered on the rising edge. This pin is shared with
WRB when the parallel mode is selected.
Read Parallel Data from Programming Registers. Shared function with CSB. Chip-select signal
associated with the serial programming bus. Active LOW. This pin is shared with RDB when
the parallel mode is selected.
Multifunction Pin According to the Mode of Operation Selected in the Programming Control Register.
If in the FSK mode logic low selects F1, logic high selects F2. If in the BPSK mode, logic low selects
Phase 1, logic high selects Phase 2. If in the Chirp mode, logic high engages the HOLD function
causing the frequency accumulator to halt at its current location. To resume or commence Chirp,
logic low is asserted.
FSK/BPSK/
HOLD
30
SHAPED
KEYING
Must First Be Selected in the Programming Control Register to Function. A logic high will cause the
I and Q DAC outputs to ramp-up from zero-scale to full-scale amplitude at a preprogrammed rate.
Logic low causes the full-scale output to ramp-down to zero-scale at the preprogrammed rate.
31, 32, 37, AVDD
38, 44, 50,
Connections for the Analog Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
and DGND
54, 60, 65
33, 34, 39, AGND
40, 41, 45,
46, 47, 53,
59, 62, 66,
67
Connections for Analog Circuitry Ground Return. Same potential as DGND.
36
VOUT
Internal High-Speed Comparator’s Noninverted Output Pin. Designed to drive 10 dBm to 50 Ω load
as well as standard CMOS logic levels.
42
43
48
49
51
52
VINP
VINN
IOUT1
IOUT1B
IOUT2B
IOUT2
Voltage Input Positive. The internal high-speed comparator’s noninverting input.
Voltage Input Negative. The internal high-speed comparator’s inverting input.
Unipolar Current Output of the I or Cosine DAC.
Complementary Unipolar Current Output of the I or Cosine DAC.
Complementary Unipolar Current Output of the Q or Sine or DAC.
Unipolar Current Output of the Q or Sine DAC. This DAC can be programmed to accept
external 12-bit data in lieu of internal sine data. This allows the AD9854 to emulate the AD9852
control DAC function.
REV. 0
–5–
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