AD9852
Test
AD9852ASVZ
AD9852ASTZ
Parameter
Temp
Level Min
Typ
Max
Min
Typ
Max
Unit
PARALLEL I/O TIMING CHARACTERISTICS
tASU (Address Setup Time to WR Signal Active)
tADHW (Address Hold Time to WR Signal Inactive)
tDSU (Data Setup Time to WR Signal Inactive)
tDHD (Data Hold Time to WR Signal Inactive)
tWRLOW (WR Signal Minimum Low Time)
tWRHIGH (WR Signal Minimum High Time)
tWR (Minimum WR Time)
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
V
8.0
0
7.5
8.0
0
7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.0
0
1.6
1.8
3.0
0
1.6
1.8
2.5
7
2.5
7
10.5
15
5
10.5
15
5
tADV (Address to Data Valid Time)
tADHR (Address Hold Time to RD Signal Inactive)
tRDLOV (RD Low to Output Valid)
15
15
IV
IV
IV
15
10
15
10
tRDHOZ (RD High to Data Three-State)
SERIAL I/O TIMING CHARACTERISTICS
tPRE (CS Setup Time)
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
V
30
100
30
40
40
0
30
100
30
40
40
0
ns
ns
ns
ns
ns
ns
ns
tSCLK (Period of Serial Data Clock)
tDSU (Serial Data Setup Time)
tSCLKPWH (Serial Data Clock Pulse Width High)
tSCLKPWL (Serial Data Clock Pulse Width Low)
tDHLD (Serial Data Hold Time)
tDV (Data Valid Time)
30
30
9
CMOS LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
POWER SUPPLY10
VS Current11
25°C
25°C
25°C
25°C
25°C
I
I
IV
IV
V
2.2
2.2
V
V
μA
μA
pF
0.8
5
5
0.8
12
12
3
3
25°C
25°C
25°C
25°C
25°C
25°C
25°C
I
I
I
I
I
I
I
815
640
585
2.70
2.12
1.93
1
922
725
660
3.20
2.52
2.29
50
585
465
425
1.93
1.53
1.40
1
660
mA
mA
mA
W
W
W
VS Current12
520
475
2.39
1.81
1.65
50
VS Current13
11
PDISS
PDISS
PDISS
12
13
PDISS Power-Down Mode
mW
1 The reference clock inputs are configured to accept a 1 V p-p (typical) dc offset square or sine waves centered at one-half the applied VDD or a 3 V TTL-level pulse input.
2 An internal 400 mV p-p differential voltage swing equates to 200 mV p-p applied to both REFCLK input pins.
3 Pipeline delays of each individual block are fixed; however, if the first eight MSBs of a tuning word are all 0s, the delay appears longer. This is due to insufficient phase
accumulation per a system clock period to produce enough LSB amplitude to the D/A converter.
4 If a feature such as inverse sinc, which has 16 pipeline delays, can be bypassed, the total delay is reduced by that amount.
5 The I/O UD CLK transfers data from the I/O port buffers to the programming registers. This transfer is measured in system clocks.
6 A change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold.
7 Represents the comparator’s inherent cycle-to-cycle jitter contribution. The input signal is a 1 V, 40 MHz square wave, and the measurement device is a Wavecrest DTS-2075.
8 Comparator input originates from analog output section via external 7-pole elliptic low-pass filter. Single-ended input, 0.5 V p-p. Comparator output terminated in 50 Ω.
9
Avoid overdriving digital inputs. (Refer to equivalent circuits in Figure 3.)
10 If all device functions are enabled, it is not recommended to simultaneously operate the device at the maximum ambient temperature of 85°C and at the maximum
internal clock frequency. This configuration may result in violating the maximum die junction temperature of 150°C. Refer to the Power Dissipation and Thermal
Considerations section for derating and thermal management information.
11 All functions engaged.
12 All functions except inverse sinc engaged.
13 All functions except inverse sinc and digital multipliers engaged.
Rev. E | Page 7 of 52
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