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AD9851BRSRL

更新时间： 2024-02-01 12:47:15
品牌 Logo 应用领域
亚德诺 - ADI 模拟IC信号电路光电二极管数据分配系统
页数 文件大小 规格书
24页 719K
描述
CMOS 180 MHz DDS/DAC Synthesizer

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AD9851BRSRL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP,针数：28
Reach Compliance Code：unknown风险等级：5.05
Is Samacsys：N模拟集成电路 - 其他类型：ANALOG CIRCUIT
JESD-30 代码：R-PDSO-G28JESD-609代码：e3
长度：10.2 mm湿度敏感等级：1
功能数量：1端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：260座面最大高度：2 mm
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：5.3 mm
Base Number Matches：1

AD9851BRSRL 数据手册

 浏览型号AD9851BRSRL的Datasheet PDF文件第1页浏览型号AD9851BRSRL的Datasheet PDF文件第2页浏览型号AD9851BRSRL的Datasheet PDF文件第4页浏览型号AD9851BRSRL的Datasheet PDF文件第5页浏览型号AD9851BRSRL的Datasheet PDF文件第6页浏览型号AD9851BRSRL的Datasheet PDF文件第7页 
AD9851  
T
e
st  
Level  
AD9851BRS  
Typ  
Parameter  
Temp  
Min  
Max  
Unit  
TIMING CHARACTERISTICS
4  
tWH, tWL (W_CLK Min PulseWidth High/Low)  
t
DS, tDH (Data toW_CLK Setup and HoldTimes)  
tFH, tFL (FQ_UD Min PulseWidth High/Low)  
t
CD (REFCLK Delay After FQ_UD)5  
tFD (FQ_UD Min Delay AfterW_CLK)  
t
CF (Output Latency from FQ_UD)  
Frequency Change  
Full  
Full  
Full  
Full  
Full  
IV  
IV  
IV  
IV  
IV  
3.5  
3.5  
7
3.5  
7
ns  
ns  
ns  
ns  
ns  
Full  
Full  
IV  
IV  
18  
13  
SYSCLK  
Cycles  
SYSCLK  
Cycles  
ns  
Phase Change  
tRH (CLKIN Delay After RESET Rising Edge)  
t
RL (RESET Falling Edge After CLKIN)  
tRR (Recovery from RESET)  
Full  
Full  
Full  
IV  
IV  
IV  
3.5  
3.5  
2
ns  
SYSCLK  
Cycles  
SYSCLK  
Cycles  
SYSCLK  
Cycles  
µs  
tRS (Minimum RESETWidth)  
Full  
Full  
25°C  
IV  
IV  
V
5
tOL (RESET Output Latency)  
13  
Wake-UpTime from Power-Down Mode6  
5
CMOS LOGIC INPUTS  
Logic 1Voltage, 5V Supply  
Logic 1Voltage, 3.3V Supply  
Logic 1Voltage, 2.7V Supply  
Logic 0Voltage  
Logic 1 Current  
Logic 0 Current  
Rise/FallTime  
Input Capacitance  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
I
3.5  
2.4  
2.0  
V
V
V
V
µA  
µA  
ns  
pF  
IV  
IV  
IV  
I
I
IV  
V
0.8  
12  
12  
100  
3
POWER SUPPLY  
V
S6 Current @:  
62.5 MHz Clock, 2.7V Supply  
100 MHz Clock, 2.7V Supply  
62.5 MHz Clock, 3.3V Supply  
125 MHz Clock, 3.3V Supply  
62.5 MHz Clock, 5V Supply  
125 MHz Clock, 5V Supply  
180 MHz Clock, 5V Supply  
Power Dissipation @ :  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
VI  
VI  
VI  
VI  
VI  
VI  
VI  
30  
40  
35  
55  
50  
70  
110  
35  
50  
45  
70  
65  
90  
130  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
62.5 MHz Clock, 5V Supply  
62.5 MHz Clock, 3.3V Supply  
62.5 MHz Clock, 2.7V Supply  
100 MHz Clock, 2.7V Supply  
125 MHz Clock, 5V Supply  
125 MHz Clock, 3.3V Supply  
180 MHz Clock, 5V Supply  
P
DISS Power-Down Mode @:  
5V Supply  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
VI  
VI  
VI  
VI  
VI  
VI  
VI  
250  
115  
85  
110  
365  
180  
555  
325  
150  
95  
135  
450  
230  
650  
mW  
mW  
mW  
mW  
mW  
mW  
mW  
25°C  
25°C  
VI  
VI  
17  
4
55  
20  
mW  
mW  
2.7V Supply  
NOTES  
1+VS collectively refers to the positive voltages applied to DVDD, PVCC, and AVDD.Voltages applied to these pins should be of the same potential.  
2Indicates the minimum signal levels required to reliably clock the device at the indicated supply voltages.This specifies the p-p signal level and dc offset needed when the  
clocking signal is not of CMOS/TTL origin, i.e., a sine wave with 0V dc offset.  
3The comparator’s jitter contribution to any input signal.This is the minimum jitter on the outputs that can be expected from an ideal input. Considerably more output  
jitter is seen when nonideal input signals are presented to the comparator inputs. Nonideal characteristics include the presence of extraneous, nonharmonic signals (spur’s,  
noise), slower slew rate, and low comparator overdrive.  
4Timing of input signals FQ_UD,WCLK, RESET are asynchronous to the reference clock; however, the presence of a reference clock is required to implement those  
functions. In the absence of a reference clock, the AD9851 automatically enters power-down mode rendering the IC, including the comparator, inoperable until a refer-  
ence clock is restored.Very high speed updates of frequency/phase word will require FQ_UD andWCLK to be externally synchronized with the external reference clock to  
ensure proper timing.  
5Not applicable when 6
REFCLK Multiplier is engaged.  
6Assumes no capacitive load on DACBP (Pin 17).  
Specifications subject to change without notice.  
RE
V
. D  
–3–  
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