AD9845AJST

更新时间： 2024-02-09 01:55:31

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
22页	250K
描述
Complete 12-Bit 30 MSPS CCD Signal Processor

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AD9845AJST 数据手册

AD9845A

DEFINITIONS OF SPECIFICATIONS

in LSB, and represents the rms noise level of the total signal

chain at the speciﬁed gain setting. The output noise can be

converted to an equivalent voltage, using the relationship 1 LSB

= (ADC Full Scale/2^Ncodes) when N is the bit resolution of the

ADC. For the AD9845A, 1 LSB is 500 µV.

DIFFERENTIAL NONLINEARITY (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Thus every code

must have a ﬁnite width. No missing codes guaranteed to 12-bit

resolution indicates that all 4096 codes, respectively, must be

present over all operating conditions.

POWER SUPPLY REJECTION (PSR)

The PSR is measured with a step change applied to the supply

pins. This represents a very high frequency disturbance on the

AD984x’s power supply. The PSR speciﬁcation is calculated

from the change in the data outputs for a given step change in

the supply voltage.

PEAK NONLINEARITY

Peak nonlinearity, a full signal chain speciﬁcation, refers to the

peak deviation of the output of the AD984x from a true straight

line. The point used as “zero scale” occurs 1/2 LSB before the

ﬁrst code transition. “Positive full scale” is deﬁned as a Level 1,

1/2 LSB beyond the last code transition. The deviation is measured

from the middle of each particular output code to the true straight

line. The error is then expressed as a percentage of the 2 V ADC

full-scale signal. The input signal is always appropriately gained up

to ﬁll the ADC’s full-scale range.

INTERNAL DELAY FOR SHP/SHD

The internal delay (also called aperture delay) is the time delay

that occurs from when a sampling edge is applied to the AD984x

until the actual sample of the input signal is held. Both SHP and

SHD sample the input signal during the transition from low to

high, so the internal delay is measured from each clock’s rising

edge to the instant the actual internal sample is taken.

TOTAL OUTPUT NOISE

The rms output noise is measured using histogram techniques.

The standard deviation of the ADC output codes is calculated

EQUIVALENT INPUT CIRCUITS

DVDD

ACVDD

330ꢀ

60ꢀ

ACVSS

DVSS

Figure 1. Digital Inputs—SHP, SHD, DATACLK, CLPOB,

CLPDM, HD, VD, PBLK, SCK, SL

Figure 3. CCDIN (Pin 30)

DRVDD

DVDD

DATA

DVDD

DATA IN

THREE-

STATE

330ꢀ

DOUT

DATA OUT

RNW

DVSS

DRVSS

DVSS

Figure 2. Data Outputs—D0–D11

Figure 4. SDATA (Pin 47)

REV. 0

–7–

1...4 5 678 9 10...22

下载PDF

与AD9845AJST相关器件

型号	品牌	描述	获取价格	数据表
AD9845AJSTRL	ADI	IC SPECIALTY CONSUMER CIRCUIT, PQFP48, PLASTIC , LQFP-48, Consumer IC:Other	获取价格
AD9845AJSTZ	ADI	IC SPECIALTY CONSUMER CIRCUIT, PQFP48, PLASTIC , LQFP-48, Consumer IC:Other	获取价格
AD9845AJSTZRL	ADI	IC SPECIALTY CONSUMER CIRCUIT, PQFP48, PLASTIC , LQFP-48, Consumer IC:Other	获取价格
AD9845B	ADI	Complete 12-Bit 30 MSPS CCD Signal Processor	获取价格
AD9845BJST	ADI	Complete 12-Bit 30 MSPS CCD Signal Processor	获取价格
AD9845BJST	ROCHESTER	暂无描述	获取价格