AD9832BRU

更新时间： 2024-02-17 15:56:02

品牌	Logo	应用领域
亚德诺 - ADI		数据分配系统
页数	文件大小	规格书
16页	149K
描述
CMOS Complete DDS

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数据手册

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AD9832BRU 数据手册

AD9832

(V = +3.3 V ؎ 10%; +5 V ؎ 10%; AGND = DGND = 0 V, unless otherwise noted)

TIMING CHARACTERISTICS

Limit at

T_MINto T_MAX

(B Version)

Parameter

Units

Test Conditions/Comments

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

ns min

ns max

ns min

MCLK Period

MCLK High Duration

MCLK Low Duration

SCLK Period

SCLK High Duration

SCLK Low Duration

FSYNC to SCLK Falling Edge Setup Time

FSYNC to SCLK Hold Time

SCLK – 5

t₉

t₁₀

t₁₁

Data Setup Time

Data Hold Time

FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge

FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge

t_11A

*See Pin Function Descriptions.

Guaranteed by design but not production tested.

t₁

MCLK

t₂

t₃

Figure 2. Master Clock

t₅

t₄

SCLK

t₇

t₈

t₆

FSYNC

t₁₀

t₉

D15

D14

D15

D14

SDATA

Figure 3. Serial Timing

MCLK

t_11A

VALID DATA

t₁₁

FSELECT

PSEL0, PSEL1

VALID DATA

Figure 4. Control Timing

REV. A

–3–

1 234 5 6 7...16

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