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AD9832BRU PDF预览

AD9832BRU

更新时间: 2024-02-13 07:48:30
品牌 Logo 应用领域
亚德诺 - ADI 数据分配系统
页数 文件大小 规格书
16页 149K
描述
CMOS Complete DDS

AD9832BRU 数据手册

 浏览型号AD9832BRU的Datasheet PDF文件第1页浏览型号AD9832BRU的Datasheet PDF文件第3页浏览型号AD9832BRU的Datasheet PDF文件第4页浏览型号AD9832BRU的Datasheet PDF文件第5页浏览型号AD9832BRU的Datasheet PDF文件第6页浏览型号AD9832BRU的Datasheet PDF文件第7页 
(VDD = +3.3 V ؎ 10%; +5 V ؎ 10%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN =  
REFOUT; RSET = 3.9 k; RLOAD = 300 for IOUT unless otherwise noted)  
AD9832–SPECIFICATIONS1  
Parameter  
AD9832B  
Units  
Test Conditions/Comments  
SIGNAL DAC SPECIFICATIONS  
Resolution  
10  
25  
4
4.5  
1.35  
Bits  
Update Rate (fMAX  
)
MSPS nom  
mA nom  
mA max  
V max  
IOUT Full Scale  
Output Compliance  
DC Accuracy  
3 V Power Supply  
Integral Nonlinearity  
Differential Nonlinearity  
±1  
±0.5  
LSB typ  
LSB typ  
DDS SPECIFICATIONS2  
Dynamic Specifications  
Signal to Noise Ratio  
50  
–53  
dB min  
dBc max  
fMCLK = 25 MHz, fOUT = 1 MHz  
fMCLK = 25 MHz, fOUT = 1 MHz  
fMCLK = 6.25 MHz, fOUT = 2.11 MHz  
5 V Power Supply  
Total Harmonic Distortion  
Spurious Free Dynamic Range (SFDR)3  
Narrow Band (±50 kHz)  
–72  
–70  
–50  
–60  
1
dBc min  
dBc min  
dBc min  
dBc typ  
ms typ  
3 V Power Supply  
Wide Band (±2 MHz)  
Clock Feedthrough  
Wake-Up Time4  
Power-Down Option  
Yes  
VOLTAGE REFERENCE  
Internal Reference @ +25°C  
TMIN to TMAX  
REFIN Input Impedance  
Reference TC  
1.21  
1.21 ± 7%  
10  
100  
300  
Volts typ  
Volts min/max  
Mtyp  
ppm/°C typ  
typ  
REFOUT Output Impedance  
LOGIC INPUTS  
VINH, Input High Voltage  
VINL, Input Low Voltage  
IINH, Input Current  
VDD – 0.9  
V min  
0.9  
10  
10  
V max  
µA max  
pF max  
CIN, Input Capacitance  
POWER SUPPLIES  
AVDD  
DVDD  
IAA  
2.97/5.5  
2.97/5.5  
5
V min/V max  
V min/V max  
mA max  
5 V Power Supply  
5 V Power Supply  
3 V Power Supply  
5 V Power Supply  
IDD  
IAA + IDD  
2.5 + 0.4/MHz  
15  
24  
350  
mA typ  
mA max  
mA max  
µA max  
5
Low Power Sleep Mode  
NOTES  
1Operating temperature range is as follows: B Version, –40°C to +85°C.  
2100% production tested.  
3fMCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, fOUT = 2.11 MHz.  
4See Figure 11. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.  
5Measured with the digital inputs static and equal to 0 V or DVDD.  
The AD9832 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenuated.  
For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF.  
Specifications subject to change without notice.  
R
SET  
3.9k  
10nF  
FS  
ADJUST  
REFOUT  
REFIN  
AVDD  
10nF  
COMP  
ON-BOARD  
REFERENCE  
FULL-SCALE  
CONTROL  
12  
IOUT  
SIN  
ROM  
10-BIT DAC  
300Ω  
50pF  
AD9832  
Figure 1. Test Circuit with Which Specifications Are Tested  
–2–  
REV. A  

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