Low Power, 12.65 mW, 2.3 V to 5.5 V,
Programmable Waveform Generator
Data Sheet
AD9833
FEATURES
GENERAL DESCRIPTION
Digitally programmable frequency and phase
12.65 mW power consumption at 3 V
0 MHz to 12.5 MHz output frequency range
28-bit resolution: 0.1 Hz at 25 MHz reference clock
Sinusoidal, triangular, and square wave outputs
2.3 V to 5.5 V power supply
No external components required
3-wire SPI interface
Extended temperature range: −40°C to +105°C
Power-down option
The AD9833 is a low power, programmable waveform generator
capable of producing sine, triangular, and square wave outputs.
Waveform generation is required in various types of sensing,
actuation, and time domain reflectometry (TDR) applications.
The output frequency and phase are software programmable,
allowing easy tuning. No external components are needed. The
frequency registers are 28 bits wide: with a 25 MHz clock rate,
resolution of 0.1 Hz can be achieved; with a 1 MHz clock rate,
the AD9833 can be tuned to 0.004 Hz resolution.
The AD9833 is written to via a 3-wire serial interface. This serial
interface operates at clock rates up to 40 MHz and is compatible
with DSP and microcontroller standards. The device operates
with a power supply from 2.3 V to 5.5 V.
10-lead MSOP package
Qualified for automotive applications
APPLICATIONS
Frequency stimulus/waveform generation
Liquid and gas flow measurement
Sensory applications: proximity, motion,
and defect detection
Line loss/attenuation
Test and medical equipment
The AD9833 has a power-down function (SLEEP). This function
allows sections of the device that are not being used to be powered
down, thus minimizing the current consumption of the part. For
example, the DAC can be powered down when a clock output is
being generated.
The AD9833 is available in a 10-lead MSOP package.
Sweep/clock generators
Time domain reflectometry (TDR) applications
FUNCTIONAL BLOCK DIAGRAM
AGND
DGND
VDD
CAP/2.5V
ON-BOARD
REFERENCE
REGULATOR
2.5V
MCLK
AVDD/
DVDD
FULL-SCALE
CONTROL
COMP
FREQ0 REG
FREQ1 REG
12
PHASE
ACCUMULATOR
(28-BIT)
SIN
ROM
10-BIT DAC
MUX
MUX
MSB
PHASE0 REG
PHASE1 REG
MUX
DIVIDE
BY 2
VOUT
MUX
CONTROL REGISTER
R
200Ω
SERIAL INTERFACE
AND
CONTROL LOGIC
AD9833
FSYNC
SCLK
SDATA
Figure 1.
Rev. E
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