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AD9833BRM PDF预览

AD9833BRM

更新时间: 2024-02-11 18:00:56
品牌 Logo 应用领域
亚德诺 - ADI 数据分配系统
页数 文件大小 规格书
18页 206K
描述
+2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS

AD9833BRM 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP10,.19,20针数:10
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.6
边界扫描:NO最大时钟频率:25 MHz
JESD-30 代码:S-PDSO-G10JESD-609代码:e3
长度:3 mm低功率模式:YES
湿度敏感等级:1端子数量:10
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP10,.19,20封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2.5/5 V认证状态:Not Qualified
座面最大高度:1.1 mm子类别:DSP Peripherals
最大供电电压:5.5 V最小供电电压:2.3 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3 mm
uPs/uCs/外围集成电路类型:DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATORBase Number Matches:1

AD9833BRM 数据手册

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PRELIMINARY TECHNICAL DATA  
+2.5 V to +5.5 V, 25 MHz Low Power  
a
Preliminary Technical Data  
CMOSCompleteDDS  
AD9833  
with a power supply from +2.3 V to +5.5 V.  
FEATURES  
+2.3 V to +5.5 V Power Supply  
25 MHz Speed  
Tiny 10-Pin µSOIC Package  
Serial Loading  
Sinusoidal/Triangular DAC Output  
Power-Down Option  
Narrowband SFDR > 72 dB  
20 mW Power Consumption at 3 V  
Capability for phase modulation and frequency modula-  
tion is provided. Frequency accuracy can be controlled to  
one part in 0.25 billion. Modulation is effected by loading  
registers through the serial interface.  
The AD9833 offers a variety of output waveforms from  
the VOUT pin. The SIN ROM can be bypassed so that a  
linear up/down ramp is output from the DAC. If the SIN  
ROM is not by-passed, a sinusoidal output is available.  
Also, if a clock output is required, the MSB of the DAC  
data can be output.  
APPLICATIONS  
Digital Modulation  
Portable Equipment  
Test Equipment  
DDS Tuning  
The digital section is internally operated at +2.5 V, irre-  
spective of the value of VDD, by an on board regulator  
which steps down VDD to +2.5 V, when VDD exceeds  
+2.5 V.  
The AD9833 has a power-down function (SLEEP). This  
allows sections of the device which are not being used to  
be powered down, thus minimising the current consump-  
tion of the part e.g the DAC can be powered down when a  
clock output is being generated.  
GENERAL DESCRIPTION  
This low power DDS device is a numerically controlled  
oscillator employing a phase accumulator, a SIN ROM  
and a 10-bit D/A converter integrated on a single  
CMOS chip. Clock rates up to 25 MHz are supported  
The AD9833 is available in a 10-pin µSOIC package.  
FUNCTIONAL BLOCK DIAGRAM  
CAP/2.5V  
VDD  
DGND  
AGND  
MCLK  
On-Board  
Reference  
Regulator  
2.5V  
AVDD/  
DVDD  
FullScale  
Control  
COMP  
FREQ0 REG  
FREQ1 REG  
12  
Phase  
Accumulator  
(28 Bit)  
SIN  
ROM  
10-Bit DAC  
MUX  
Σ
MUX  
MSB  
PHASE0 REG  
PHASE1 REG  
MUX  
DIV BY  
2
MUX  
VOUT  
Control Register  
R
200  
Serial Interface  
&
AD9833  
Control Logic  
FSYNC  
SCLK  
SDATA  
REV PrG 02/02  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© Analog Devices, Inc., 2002  

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