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AD9824KCPZRL PDF预览

AD9824KCPZRL

更新时间： 2024-02-26 12:07:25
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
25页 466K
描述
Complete 14-Bit 30 MSPS CCD Signal Processor

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AD9824KCPZRL 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Contact Manufacturer零件包装代码：QFN
包装说明：VQCCN,针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.31.00.01风险等级：5.02
模拟集成电路 - 其他类型：ANALOG CIRCUITJESD-30 代码：S-XQCC-N48
JESD-609代码：e3长度：7 mm
湿度敏感等级：3功能数量：1
端子数量：48最高工作温度：85 °C
最低工作温度：-20 °C封装主体材料：UNSPECIFIED
封装代码：VQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, VERY THIN PROFILE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：0.9 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
温度等级：OTHER端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：7 mmBase Number Matches：1

AD9824KCPZRL 数据手册

 浏览型号AD9824KCPZRL的Datasheet PDF文件第17页浏览型号AD9824KCPZRL的Datasheet PDF文件第18页浏览型号AD9824KCPZRL的Datasheet PDF文件第19页浏览型号AD9824KCPZRL的Datasheet PDF文件第21页浏览型号AD9824KCPZRL的Datasheet PDF文件第22页浏览型号AD9824KCPZRL的Datasheet PDF文件第23页 
AD9824  
A/D Converter  
The VGA gains up the signal level with respect to the 0.4 V bias  
level. Signal levels above the bias level will be further increased  
to a higher ADC code, while signal levels below the bias level  
will be further decreased to a lower ADC code.  
The AD9824 uses high performance ADC architecture, opti-  
mized for high speed and low power. Differential nonlinearity  
(DNL) performance is typically better than 0.5 LSB, as shown in  
TPC 2. Instead of the 1 V full-scale range used by the earlier  
AD9801 and AD9803 products from Analog Devices, the  
AD9824’s ADC uses a 2 V input range. Better noise perfor-  
mance results from using a larger ADC full-scale range  
(see TPC 3).  
AUX2 Mode  
For sampling video-type waveforms, such as NTSC and PAL  
signals, the AUX2 channel provides black level clamping, gain  
adjustment, and A/D conversion. Figure 31 shows the circuit  
configuration for using the AUX2 channel input (Pin 34). An  
external 0.1 µF blocking capacitor is used with the on-chip video  
clamp circuit to level shift the input signal to a desired refer-  
ence level. The clamp circuit automatically senses the most  
negative portion of the input signal and adjusts the voltage  
across the input capacitor. This forces the black level of the  
input signal to be equal to the value programmed into the Clamp  
Level Register (see Serial Interface Timing and Internal Register  
Description). The VGA provides gain adjustment from 0 dB to  
18 dB. The same VGA Gain Register is used, but only the  
9 MSBs of the gain register are used (see Table VII.)  
AUX1 Mode  
For applications that do not require CDS, the AD9824 can be  
configured to sample ac-coupled waveforms. Figure 30 shows  
the circuit configuration for using the AUX1 channel input  
(Pin 36). A single 0.1 µF ac-coupling capacitor is needed between  
the input signal driver and the AUX1IN pin. An on-chip dc-bias  
circuit sets the average value of the input signal to approximately  
0.4 V, which is referenced to the midscale code of the ADC.  
The VGA Gain Register provides a gain range of 0 dB to 36 dB in  
this mode of operation (see VGA Gain Curve, Figure 29).  
0.4V  
0.8V  
??V  
0dB TO 36dB  
5kꢁ  
0.1ꢂF  
AUX1IN  
INPUT SIGNAL  
VGA  
ADC  
MIDSCALE  
10  
0.4V  
0.4V  
VGA GAIN  
REGISTER  
Figure 30. AUX1 Circuit Configuration  
VGA GAIN  
REGISTER  
9
0dB TO 18dB  
BUFFER  
AUX2IN  
VIDEO  
SIGNAL  
ADC  
VGA  
0.1ꢂF  
CLAMP LEVEL  
VIDEO CLAMP  
CIRCUIT  
LPF  
CLAMP LEVEL  
REGISTER  
8
Figure 31. AUX2 Circuit Configuration  
Table VII. VGA Gain Register Used for AUX2-Mode  
MSB  
D9  
LSB  
D0  
D10  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Gain (dB)  
X
0
1
X
0
X
0
X
0
X
0
•
X
0
X
0
X
0
X
0
X
0
0.0  
0.0  
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
18.0  
REV. 0  
–19–  
1...17181920212223...25

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