Datasheet > AD9824KCPZRL

AD9824KCPZRL

更新时间： 2024-01-15 10:45:14

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
25页	466K
描述
Complete 14-Bit 30 MSPS CCD Signal Processor

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技术参数
数据手册

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AD9824KCPZRL 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Contact Manufacturer	零件包装代码：	QFN
包装说明：	VQCCN,	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	风险等级：	5.02
模拟集成电路 - 其他类型：	ANALOG CIRCUIT	JESD-30 代码：	S-XQCC-N48
JESD-609代码：	e3	长度：	7 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-20 °C	封装主体材料：	UNSPECIFIED
封装代码：	VQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	0.9 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3 V	表面贴装：	YES
温度等级：	OTHER	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	7 mm	Base Number Matches：	1

AD9824KCPZRL 数据手册

AD9824

Variable Gain Ampliﬁer

MOSAIC SEPARATE COLOR

STEERING MODE

CCD: PROGRESSIVE BAYER

The VGA stage provides a gain range of 2 dB to 36 dB, program-

mable with 10-bit resolution through the serial digital interface.

Combined with approximately 4 dB from the PxGA stage, the

total gain range for the AD9824 is 6 dB to 40 dB. The minimum

gain of 6 dB is needed to match -a 1 V input signal with the

ADC full-scale range of 2 V. When compared to 1 V full-scale

systems (such as ADI’s AD9803), the equivalent gain range is

0 dB to 34 dB.

LINE0

LINE1

LINE2

GAIN0, GAIN1, GAIN0, GAIN1...

GAIN2, GAIN3, GAIN2, GAIN3...

GAIN0, GAIN1, GAIN0, GAIN1...

Figure 26. CCD Color Filter Example: Progressive Scan

The VGA gain curve follows a “linear-in-dB” shape. The exact

VGA gain can be calculated for any gain register value by using

the following equation:

CCD: INTERLACED BAYER

EVEN FIELD

VD SELECTED COLOR

STEERING MODE

LINE0

LINE1

LINE2

GAIN0, GAIN1, GAIN0, GAIN1...

Code Range Gain Equation (dB)

0–1023

Gain = (0.0353)(Code)

As shown in the CCD Mode Speciﬁcations, only the VGA gain

range from 2 dB to 36 dB has tested and guaranteed accuracy.

This corresponds to a VGA gain code range of 77 to 1023. The

Gain Accuracy Speciﬁcations also include a PxGA gain of approxi-

mately 3.3 dB, for a total gain range of 6 dB to 40 dB.

ODD FIELD

LINE0

LINE1

LINE2

GAIN2, GAIN3, GAIN2, GAIN3...

Figure 27. CCD Color Filter Example: Interlaced

The same Bayer pattern can also be interlaced, and the VD

selected mode should be used with this type of CCD (see

Figure 27). The color steering performs the proper multiplexing

of the R, G, and B gain values (loaded into the PxGA gain regis-

ters) and is synchronized by the user with vertical (VD) and

horizontal (HD) sync pulses. For more detailed information, see

the PxGA Timing section. The PxGA gain for each of the four

channels is variable from –2.5 dB to +9.5 dB, controlled in 64

steps through the serial interface. The PxGA gain curve is

shown in Figure 28.

127

255

383

511

639

767

895

1023

VGA GAIN REGISTER CODE

Figure 29. VGA Gain Curve (Gain from PxGA Not Included)

Optical Black Clamp

The optical black clamp loop is used to remove residual offsets

in the signal chain and to track low frequency variations in the

CCD’s black level. During the optical black (shielded) pixel

interval on each line, the ADC output is compared with a ﬁxed

black level reference, selected by the user in the clamp level

256 steps. The resulting error signal is ﬁltered to reduce noise,

and the correction value is applied to the ADC input through a

D/A converter. Normally, the optical black clamp loop is turned

on once per horizontal line, but this loop can be updated more

slowly to suit a particular application. If external digital clamping

is used during the post processing, the AD9824 optical black

clamping may be disabled using Bit D5 in the Operation Register

(see Serial Interface Timing and Internal Register Description

section). When the loop is disabled, the clamp level register may

still be used to provide programmable offset adjustment.

–2

–4

(011111)

(100000)

PxGA GAIN REGISTER CODE

Horizontal timing is shown in Figure 6. The CLPOB pulse

should be placed during the CCD’s optical black pixels. It is

recommended that the CLPOB pulse duration be at least 20

pixels wide to minimize clamp noise. Shorter pulsewidths may be

used, but clamp noise may increase and the ability to track

low frequency variations in the black level will be reduced.

Figure 28. PxGA Gain Curve

–18–

REV. 0

1...16 17 181920 21 22...25

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