11-Bit, 105 MSPS/150 MSPS, 1.8 V
Dual Analog-to-Digital Converter
AD9627-11
FEATURES
FUNCTIONAL BLOCK DIAGRAM
SDIO/SCLK/
SNR = 65.8 dBc (66.8 dBFS) to 70 MHz @ 105 MSPS
SFDR = 85 dBc to 70 MHz @ 105 MSPS
Low power: 600 mW @ 105 MSPS
SNR = 65.7 dBc (66.7 dBFS) to 70 MHz @ 150 MSPS
SFDR = 84 dBc to 70 MHz @ 150 MSPS
Low power: 820 mW @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3V CMOS output supply or 1.8 V LVDS
output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
AVDD DVDD
FD(0:3)A
DCS DFS CSB DRVDD
FD BITS/THRESHOLD
DETECT
SPI
D10A
D0A
PROGRAMMING DATA
VIN+A
VIN–A
SHA
ADC
SIGNAL
MONITOR
CLK+
VREF
CLK–
SENSE
DIVIDE
DCOA
1 TO 8
DCO
GENERATION
CML
REF
SELECT
DCOB
D10B
DUTY CYCLE
STABILIZER
RBIAS
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
D0B
VIN–B
VIN+B
SHA
ADC
SIGNAL MONITOR
DATA
AD9627-11
95 dB channel isolation/crosstalk
Serial port control
MULTICHIP
SYNC
FD BITS/THRESHOLD SIGNAL MONITOR
DETECT
INTERFACE
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated receive features
Fast detect/threshold bits
Composite signal monitor
AGND SYNC
FD(0:3)B
SMI
SMI
SMI DRGND
SDFS SCLK/ SDO/
PDWN OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
Figure 1.
APPLICATIONS
Communications
PRODUCT HIGHLIGHTS
1. Integrated dual, 11-bit, 105 MSPS/150 MSPS ADC.
Diversity radio systems
Multimode digital receivers (3G)
GSM, EDGE, WCDMA, CDMA2000,
WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
2. Fast overrange detect and signal monitor with serial output.
3. Signal monitor block with dedicated serial output mode.
4. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 450 MHz.
5. Operation from a single 1.8 V supply and a separate digital
output driver supply to accommodate 1.8 V to 3.3 V logic
families.
6. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
7. Pin compatibility with the AD9640, AD9627, and AD9600
for a simple migration from 11 bits to 14 bits, 12 bits, or
10 bits.
Rev. A
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