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AD9627_17

更新时间: 2024-02-16 08:05:13
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亚德诺 - ADI /
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77页 2315K
描述
1.8 V Dual Analog-to-Digital Converter

AD9627_17 数据手册

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12-Bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS,  
1.8 V Dual Analog-to-Digital Converter  
AD9627  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
SDIO/SCLK/  
SNR = 69.4 dBc (70.4 dBFS) to 70 MHz @ 125 MSPS  
SFDR = 85 dBc to 70 MHz @ 125 MSPS  
Low power: 750 mW @ 125 MSPS  
SNR = 69.2 dBc (70.2 dBFS) to 70 MHz @ 150 MSPS  
SFDR = 84 dBc to 70 MHz @ 150 MSPS  
Low power: 820 mW @ 150 MSPS  
1.8 V analog supply operation  
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS  
output supply  
Integer 1-to-8 input clock divider  
IF sampling frequencies to 450 MHz  
Internal ADC voltage reference  
AVDD DVDD  
FD(0:3)A  
DCS DFS CSB DRVDD  
FD BITS/THRESHOLD  
DETECT  
SPI  
D11A  
D0A  
PROGRAMMING DATA  
VIN+A  
VIN–A  
SHA  
ADC  
SIGNAL  
MONITOR  
CLK+  
VREF  
CLK–  
SENSE  
DIVIDE  
DCOA  
1 TO 8  
DCO  
GENERATION  
CML  
REF  
SELECT  
DCOB  
D11B  
DUTY CYCLE  
STABILIZER  
RBIAS  
Integrated ADC sample-and-hold inputs  
Flexible analog input range: 1 V p-p to 2 V p-p  
Differential analog inputs with 650 MHz bandwidth  
ADC clock duty cycle stabilizer  
D0B  
VIN–B  
VIN+B  
SHA  
ADC  
SIGNAL MONITOR  
DATA  
AD9627  
95 dB channel isolation/crosstalk  
Serial port control  
MULTICHIP  
SYNC  
FD BITS/THRESHOLD SIGNAL MONITOR  
DETECT  
INTERFACE  
User-configurable, built-in self-test (BIST) capability  
Energy-saving power-down modes  
Integrated receive features  
AGND SYNC  
FD(0:3)B  
SMI  
SMI  
SMI DRGND  
SDFS SCLK/ SDO/  
PDWN OEB  
NOTES  
Fast detect/threshold bits  
1.PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;  
SEE FIGURE 7 FOR LVDS PIN NAMES.  
Composite signal monitor  
Figure 1.  
APPLICATIONS  
Communications  
PRODUCT HIGHLIGHTS  
Diversity radio systems  
Multimode digital receivers (3G)  
GSM, EDGE, WCDMA,  
1. Integrated dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/  
150 MSPS ADC.  
2. Fast overrange detect and signal monitor with serial output.  
3. Signal monitor block with dedicated serial output mode.  
4. Proprietary differential input that maintains excellent SNR  
performance for input frequencies up to 450 MHz.  
5. Operation from a single 1.8 V supply and a separate digital  
output driver supply to accommodate 1.8 V to 3.3 V logic  
families.  
CDMA2000, WiMAX, TD-SCDMA  
I/Q demodulation systems  
Smart antenna systems  
General-purpose software radios  
Broadband data applications  
6. Standard serial port interface (SPI) that supports various  
product features and functions, such as data formatting  
(offset binary, twos complement, or gray coding), enabling  
the clock DCS, power-down, test modes, and voltage  
reference mode.  
7. Pin compatibility with the AD9640, AD9627-11, and AD9600  
for a simple migration from 12 bits to 14 bits, 11 bits, or  
10 bits.  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
www.analog.com  
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.  
 
 
 
 

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