Data Sheet
AD9554
Table 150. EEPROM Storage Sequence for APLL Calibration
Address
Bits
Bit Name
Description
0x0E5E
[7:0]
IO_UPDATE
The default value of this register is 0x80, which is an IO_UPDATE instruction. The controller stores
0x80 in the EEPROM and increments the EEPROM address pointer.
0x0E5F
0x0E60
[7:0]
[7:0]
Calibrate APLLs The default value of this register is 0x92, which is a calibrate instruction for all of the APLLs. The
controller stores 0x92 in the EEPROM and increments the EEPROM address pointer.
Sync outputs
The default value of this register is 0xA0, which is a distribution sync instruction for all of the output
dividers. The controller stores 0xA0 in the EEPROM and increments the EEPROM address pointer.
Table 151. EEPROM Storage Sequence for End of Data
Address
Bits
Bit Name
Description
0x0E61
[7:0]
End of data
The default value of this register is 0xFF, which is an end of data instruction. The controller stores
this instruction, as well as four CRC-32 bytes in the EEPROM, resets the EEPROM address pointer,
and enters an idle state. Note that if the user replaces this command with a pause rather than an
end instruction, the controller actions are the same except that the controller increments the
EEPROM address pointer rather than resetting it. This allows the user to store multiple EEPROM
profiles in the EEPROM.
Table 152. Unused
Address
Bits
Bit Name
Description
0x0E62 to
0x0E6F
[7:0]
Unused
This area is unused in the default configuration and is available for additional EEPROM storage
sequence commands. Note that the EEPROM storage sequence must always end with either an end
of data or pause command.
Table 153. VCAL Reference Settings
Address
Bits
Bit Name
Description
0x0FFF
[7:0] VCAL reference access
Writing 0xF9 to this register allows access to VCAL reference registers at Register 0x1488,
Register 0x1588, Register 0x1688, and Register 0x1788. Set this register back to 0x00
after writing to Register 0x1488, Register 0x1588, Register 0x1688, and Register 0x1788
to avoid accidental writes above Register 0x0FFF.
0x00 (and all other values except 0xF9) = access disabled. Default: 0x00.
0xF9 = access enabled.
Default: 00000b.
0x1488
[7:3] Reserved
[2:1] APLL_0 manual cal level
APLL_0 reference voltage used during APLL_0 calibration. Set these bits (and issue an
IO_UPDATE by writing Register 0x000F = 0x01) before calibrating the APLLs to ensure
optimal performance over temperature and voltage extremes. These bits must be set
only once per power cycle. Before writing to this register, Register 0x0FFF must be 0xF9.
00b = Reference Voltage 0 (default).
01b = Reference Voltage 1 (recommended).
10b = Reference Voltage 2.
11b = Reference Voltage 3.
0
En APLL_0 man cal level
Enables manual control of the VCAL reference setting for APLL_0.
0 = manual control disabled (default).
1 = manual control enabled (recommended).
Default: 00000b.
0x1588
[7:3] Reserved
[2:1] APLL_1 manual cal level
APLL_1 reference voltage used during APLL_0 calibration. Set these bits (and issue an
IO_UPDATE by writing Register 0x000F = 0x01) before calibrating the APLLs to ensure
optimal performance over temperature and voltage extremes. These bits must be set
only once per power cycle. Before writing to this register, Register 0x0FFF must be 0xF9.
00b = Reference Voltage 0 (default).
01b = Reference Voltage 1 (recommended).
10b = Reference Voltage 2.
11b = Reference Voltage 3.
0
En APLL_1 man cal level
Enables manual control of the VCAL reference setting for APLL_1.
0 = manual control disabled (default).
1 = manual control enabled (recommended).
Rev. D | Page 111 of 116
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