AD9554
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital PLL (DPLL) Core .......................................................... 35
Loop Control State Machine..................................................... 38
System Clock (SYSCLK)................................................................ 39
SYSCLK Inputs ........................................................................... 39
SYSCLK Multiplier..................................................................... 39
Output Analog PLL (APLL).......................................................... 41
APLL Configuration .................................................................. 41
APLL Calibration ....................................................................... 41
Clock Distribution.......................................................................... 42
Clock Dividers ............................................................................ 42
Output Amplitude and Power-Down...................................... 42
Clock Distribution Synchronization........................................ 43
Status and Control.......................................................................... 44
Multifunction Pins (M0 to M9) ............................................... 44
IRQ Function.............................................................................. 44
Watchdog Timer......................................................................... 45
EEPROM ..................................................................................... 45
Serial Control Port ......................................................................... 49
SPI/IꢀC Port Selection................................................................ 49
SPI Serial Port Operation.......................................................... 49
IꢀC Serial Port Operation.......................................................... 52
Programming the Input/Output Registers.................................. 55
Buffered/Active Registers.......................................................... 55
Write Detect Registers ............................................................... 55
Autoclear Registers..................................................................... 55
Register Access Restrictions...................................................... 55
Thermal Performance.................................................................... 56
Power Supply Partitions................................................................. 57
VDD Supplies ............................................................................. 57
VDD_SP Supply ......................................................................... 57
Register Map ................................................................................... 58
Register Map Bit Descriptions...................................................... 70
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 4
Specifications..................................................................................... 5
Supply Voltage............................................................................... 5
Supply Current.............................................................................. 5
Power Dissipation......................................................................... 6
System Clock Inputs (XOA, XOB) ............................................. 6
Reference Inputs ........................................................................... 7
Reference Monitors ...................................................................... 8
Reference Switchover Specifications.......................................... 8
Distribution Clock Outputs ........................................................ 9
Time Duration of Digital Functions ........................................ 11
Digital PLL (DPLL_0, DPLL_1, DPLL_2, and DPLL_3)...... 11
Analog PLL (APLL_0, APLL_1, APLL_2, and APLL_3)...... 11
Digital PLL Lock Detection ...................................................... 12
Holdover Specifications............................................................. 12
Serial Port Specifications—Serial Port Interface (SPI) Mode12
Serial Port Specifications—I2C Mode...................................... 13
RESET
Logic Inputs (
, M9 to M0)............................................. 14
Logic Outputs (M9 to M0)........................................................ 14
Jitter Generation ......................................................................... 15
Absolute Maximum Ratings.......................................................... 16
ESD Caution................................................................................ 16
Pin Configuration and Function Descriptions........................... 17
Typical Performance Characteristics ........................................... 21
Input/Output Termination Recommendations.......................... 24
Getting Started................................................................................ 25
Chip Power Monitor and Startup............................................. 25
Multifunction Pins at Reset/Power-Up ................................... 25
Device Register Programming Using a Register Setup File.. 25
Register Programming Overview............................................. 30
Theory of Operation ...................................................................... 33
Overview...................................................................................... 33
Reference Input Physical Connections.................................... 34
Reference Monitors .................................................................... 34
Reference Input Block................................................................ 34
Reference Switchover................................................................. 35
Serial Control Port Configuration (Register 0x0000 to
Register 0x0001)......................................................................... 70
Clock Part Family ID (Register 0x0003 to Register 0x0006) 71
SPI Version (Register 0x000B).................................................. 71
Vendor ID (Register 0x000C to Register 0x000D) ................ 71
IO_Update (Register 0x000F)................................................... 71
User Scratchpad (Register 0x00FE to Register 0x00FF) ....... 71
Rev. D | Page 2 of 116
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