5秒后页面跳转
AD9551BCPZ PDF预览

AD9551BCPZ

更新时间: 2024-01-14 06:21:07
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
40页 793K
描述
Multiservice Clock Generator

AD9551BCPZ 数据手册

 浏览型号AD9551BCPZ的Datasheet PDF文件第33页浏览型号AD9551BCPZ的Datasheet PDF文件第34页浏览型号AD9551BCPZ的Datasheet PDF文件第35页浏览型号AD9551BCPZ的Datasheet PDF文件第37页浏览型号AD9551BCPZ的Datasheet PDF文件第38页浏览型号AD9551BCPZ的Datasheet PDF文件第39页 
AD9551  
REFA Frequency Control (Register 0x1E to Register 0x25)  
Table 29.  
Address  
Bit  
Bit Name  
Description  
0x1E  
7
Enable SPI control of  
REFA SDM  
Controls REFA frequency division functionality.  
0 = REFA frequency division, as defined by the A[3:0] pins (default).  
1 = contents of Register 0x1F to Register 0x25 define REFA frequency division via NA,  
MODA, and FRACA.  
6
5
4
Bypass REFA SDM  
Enable REFA SDM  
Enable REFB  
Controls bypassing of the REFA SDM.  
0 = allow integer-plus-fractional division (default).  
1 = allow only integer division.  
Controls REFA SDM enable and hold functionality.  
0 = reset REFA SDM and stop its clocks.  
1 = REFA SDM enabled (default).  
Controls REFB enable and power-down functionality.  
0 = power down REFB input receiver (ineffective unless Register 0x1A[1] = 1).  
1 = normal operation (default).  
3
2
Unused  
Unused.  
Disable REF SDM PRBS  
Controls the PRBS generator for both the REFA and REFB SDMs.  
0 = PRBS generator enabled (default).  
1 = PRBS generator disabled.  
[1:0]  
Select 19.44 MHz input  
mode divider  
Selects the divider value when the 19.44 MHz input mode is in effect.  
00 = 1 (default).  
01 = 1.  
10 = 2.  
11 = 4.  
These bits are ineffective unless the A[3:0] pins = 1111 or the B[3:0] pins = 1111.  
0x1F  
0x20  
0x21  
[7:0] FRACA  
[7:0] FRACA  
[7:4] FRACA  
Bits[19:12] of the 20-bit fractional part of the REFA SDM.  
Bits[11:4] of the 20-bit fractional part of the REFA SDM.  
Bits[3:0] of the 20-bit fractional part of the REFA SDM.  
Default is FRACA = 0100 0000 0000 0000 0000 (262,144).  
Note that FRACA assumes twos complement format.  
[3:0] Unused  
[7:2] NA  
Unused.  
0x22  
0x23  
6-bit integer divide value for the REFA SDM. Default divide value is 16.  
Unused.  
[1:0] Unused  
7
Unused  
This bit must be programmed to 0, even though the default value is 1.  
Bits[18:12] of the 19-bit modulus of the REFA SDM.  
Bits[11:4] of the 19-bit modulus of the REFA SDM.  
[6:0] MODA  
[7:0] MODA  
[7:4] MODA  
0x24  
0x25  
Bits[3:0] of the 19-bit modulus of the REFA SDM.  
Default is MODA = 000 0000 0000 0000 0000.  
[3:0] Unused  
Unused.  
Rev. B | Page 36 of 40  

与AD9551BCPZ相关器件

型号 品牌 获取价格 描述 数据表
AD9551BCPZ-REEL7 ADI

获取价格

Multiservice Clock Generator
AD9552 ADI

获取价格

Oscillator Frequency Upconverter
AD9552BCPZ ADI

获取价格

Oscillator Frequency Upconverter
AD9552BCPZ-REEL7 ADI

获取价格

Oscillator Frequency Upconverter
AD9552PCBZ ADI

获取价格

Oscillator Frequency Upconverter
AD9553 ADI

获取价格

Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet
AD9553/PCBZ ADI

获取价格

Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet
AD9553BCPZ ADI

获取价格

Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet
AD9553BCPZ-REEL7 ADI

获取价格

Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet
AD9554 ADI

获取价格

Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator