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AD9520-2/PCBZ

更新时间： 2024-01-02 19:03:48
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
84页 1688K
描述
12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO

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中文翻译

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AD9520-2/PCBZ 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.28
JESD-30 代码：S-XQCC-N64JESD-609代码：e3
长度：9 mm湿度敏感等级：1
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C最大输出时钟频率：250 MHz
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260主时钟/晶体标称频率：33.33 MHz
认证状态：Not Qualified座面最大高度：1 mm
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：9 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

AD9520-2/PCBZ 数据手册

 浏览型号AD9520-2/PCBZ的Datasheet PDF文件第77页浏览型号AD9520-2/PCBZ的Datasheet PDF文件第78页浏览型号AD9520-2/PCBZ的Datasheet PDF文件第79页浏览型号AD9520-2/PCBZ的Datasheet PDF文件第81页浏览型号AD9520-2/PCBZ的Datasheet PDF文件第82页浏览型号AD9520-2/PCBZ的Datasheet PDF文件第83页 
AD9520-2  
Table 57. System  
Reg.  
Addr  
(Hex) Bit(s) Name  
Description  
230 [3]  
230 [2]  
230 [1]  
230 [0]  
Disable power-on SYNC  
Power-on SYNC mode. Used to disable the antiruntpulse circuitry.  
[3] = 0; enable the antiruntpulse circuitry (default).  
[3] = 1; disable the antiruntpulse circuitry.  
Power-down SYNC  
Powers down the SYNC function.  
[2] = 0; normal operation of the SYNC function (default).  
[2] = 1; power-down SYNC circuitry.  
Power-down distribution reference  
Soft SYNC  
Powers down the reference for the distribution section.  
[1] = 0; normal operation of the reference for the distribution section (default).  
[1] = 1; powers down the reference for the distribution section.  
The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit  
is reversed; that is, a high level forces selected channels into a predetermined static  
state, and a 1-to-0 transition triggers a SYNC.  
[0] = 0; same as SYNC high.  
[0] = 1; same as SYNC low.  
Table 58. Update All Registers  
Reg.  
Addr  
(Hex) Bit(s) Name  
Description  
232 [0] IO_UPDATE  
This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens  
on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0.  
[0] = 1 (self-clearing); update all active registers to the contents of the buffer registers.  
Table 59. EEPROM Buffer Segment  
Reg.  
Addr  
(Hex) Bit(s) Name  
Description  
A00 to [7:0] EEPROM Buffer  
The EEPROM buffer segment section stores the starting address and number of bytes that are to be  
stored and read back to and from the EEPROM. Because the AD9520 register space is noncontiguous,  
the EEPROM controller needs to know the starting address and number of bytes in the AD9520 register  
A16  
Segment Register 1  
to EEPROM Buffer  
Segment Register 23 space to store and retrieve from the EEPROM. In addition, there are special instructions for the EEPROM  
controller, operational codes (that is, IO_UPDATE and end-of-data) that are also stored in the EEPROM  
buffer segment. The on-chip default setting of the EEPROM buffer segment registers is designed such  
that all registers are transferred to/from the EEPROM, and an IO_UPDATE is issued after transfer. See the  
Programming the EEPROM Buffer Segment section for more information.  
Rev. 0 | Page 80 of 84  
1...7778798081828384

中文翻译

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