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AD9518-4BCPZ PDF预览

AD9518-4BCPZ

更新时间: 2024-01-12 06:50:55
品牌 Logo 应用领域
亚德诺 - ADI 驱动逻辑集成电路
页数 文件大小 规格书
64页 757K
描述
6-Output Clock Generator with Integrated 1.6 GHz VCO

AD9518-4BCPZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:48
Reach Compliance Code:unknown风险等级:5.67
系列:9518输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-XQCC-N48JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:6功能数量:1
反相输出次数:端子数量:48
实输出次数:6最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):240
传播延迟(tpd):1.18 ns认证状态:COMMERCIAL
Same Edge Skew-Max(tskwd):0.22 ns座面最大高度:1 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:7 mm最小 fmax:2950 MHz
Base Number Matches:1

AD9518-4BCPZ 数据手册

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AD9518-4  
REVISION HISTORY  
1/10—Rev. 0 to Rev. A  
Changes to Clock Distribution Section........................................34  
Change to Table 32; Change to Channel Frequency  
Added 48-Lead LFCSP Package (CP-48-8) .................... Universal  
Changes to Features, Applications, and General Description.....1  
Change to CPRSET Pin Resistor Parameter..................................4  
Changes to VCP Supply Parameter.................................................11  
Changes to Table 18 ........................................................................13  
Added Exposed Paddle Notation to Figure 4;  
Changes to Table 19 ........................................................................14  
Change to High Frequency Clock Distribution—CLK or  
External VCO > 1600 MHz Section; Change to Table 21..........22  
Changes to Table 23 ........................................................................24  
Change to Configuration and Register Settings Section............25  
Change to Phase Frequency Detector (PFD) Section ................26  
Changes to Charge Pump (CP), On-Chip VCO, PLL  
External Loop Filter, and PLL Reference Inputs Sections .........27  
Change to Figure 31; Added Figure 32.........................................27  
Changes to Reference Switchover and Prescaler Sections .........28  
Changes to A and B Counters Section and Table 27 ..................29  
Change to Holdover Section..........................................................31  
Changes to VCO Calibration Section...........................................33  
Division (0, 1, and 2) Section ........................................................35  
Change to Write Section ................................................................40  
Change to Figure 46........................................................................42  
Added Thermal Performance Section; Added Table 41 ............44  
Changes to 0x003 Register Address..............................................45  
Changes to Table 43 ........................................................................47  
Changes to Table 44 ........................................................................48  
Changes to Table 45 ........................................................................55  
Changes to Table 46 ........................................................................57  
Changes to Table 47 ........................................................................58  
Changes to Table 48 ........................................................................59  
Added Frequency Planning Using the AD9518 Section............60  
Changes to LVDS Clock Distribution Section ............................61  
Changes to Figure 52 and Figure 54; Added Figure 53..............61  
Added Exposed Paddle Notation to Outline Dimensions;  
Changes to Ordering Guide...........................................................62  
9/07—Revision 0: Initial Version  
Rev. A | Page 3 of 64  
 

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