5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 时钟驱动器> AD9518-4A-PCBZ
AD9518-4A-PCBZ PDF预览

AD9518-4A-PCBZ

更新时间： 2024-02-02 18:13:25
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
64页 985K
描述
6-Output Clock Generator with Integrated 1.6 GHz VCO

阅读下载

获取价格

AD9518-4A-PCBZ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：48
Reach Compliance Code：unknown风险等级：5.67
系列：9518输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-XQCC-N48JESD-609代码：e3
长度：7 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
湿度敏感等级：6功能数量：1
反相输出次数：端子数量：48
实输出次数：6最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：240
传播延迟（tpd）：1.18 ns认证状态：COMMERCIAL
Same Edge Skew-Max（tskwd）：0.22 ns座面最大高度：1 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：7 mm最小 fmax：2950 MHz
Base Number Matches：1

AD9518-4A-PCBZ 数据手册

 浏览型号AD9518-4A-PCBZ的Datasheet PDF文件第1页浏览型号AD9518-4A-PCBZ的Datasheet PDF文件第2页浏览型号AD9518-4A-PCBZ的Datasheet PDF文件第3页浏览型号AD9518-4A-PCBZ的Datasheet PDF文件第5页浏览型号AD9518-4A-PCBZ的Datasheet PDF文件第6页浏览型号AD9518-4A-PCBZ的Datasheet PDF文件第7页 
AD9518-4  
Data Sheet  
SPECIFICATIONS  
Typical values are given for VS = VS_LVPECL = 3.3 V 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted.  
Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation.  
POWER SUPPLY REQUIREMENTS  
Table 1.  
Parameter  
Min  
3.135  
2.375  
VS  
Typ  
Max  
3.465  
VS  
Unit  
V
V
V
kΩ  
kΩ  
Test Conditions/Comments  
3.3 V 5ꢀ  
Nominally 2.5 V to 3.3 V 5ꢀ  
Nominally 3.3 V to 5.0 V 5ꢀ  
Sets internal biasing currents; connect to ground  
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);  
actual current can be calculated by CP_lsb = 3.06/CPRSET;  
connect to ground  
VS  
VS_LVPECL  
VCP  
RSET Pin Resistor  
CPRSET Pin Resistor  
3.3  
5.25  
4.12  
5.1  
2.7  
10  
BYPASS Pin Capacitor  
220  
nF  
Bypass for internal LDO regulator; necessary for LDO stability;  
connect to ground  
PLL CHARACTERISTICS  
Table 2.  
Parameter  
Min  
1450  
0.5  
Typ  
Max  
Unit  
Test Conditions/Comments  
VCO (ON-CHIP)  
Frequency Range  
1800  
MHz  
MHz/V  
V
See Figure 11  
See Figure 6  
VCO Gain (KVCO  
)
50  
Tuning Voltage (VT)  
VCP  
0.5  
−
VCP ≤ VS when using internal VCO; outside of this range, the CP  
spurs may increase due to CP up/down mismatch  
Frequency Pushing (Open-Loop)  
Phase Noise at 100 kHz Offset  
Phase Noise at 1 MHz Offset  
REFERENCE INPUTS  
1
MHz/V  
dBc/Hz f = 1625 MHz  
dBc/Hz f = 1625 MHz  
−109  
−128  
REFIN  
Differential mode (can accommodate single-ended input  
Differential Mode (REFIN,  
)
by ac grounding undriven input)  
Input Frequency  
0
250  
MHz  
Frequencies below about 1 MHz should be dc-coupled;  
be careful to match VCM (self-bias voltage)  
Input Sensitivity  
250  
mV p-p PLL figure of merit (FOM) increases with increasing slew rate  
(see Figure 10); the input sensitivity is sufficient for ac-coupled  
LVPECL and LVDS signals  
Self-Bias Voltage, REFIN  
REFIN  
1.35  
1.30  
4.0  
1.60  
1.50  
4.8  
1.75  
1.60  
5.9  
V
V
Self-bias voltage of REFIN1  
Self-Bias Voltage,  
Input Resistance, REFIN  
REFIN  
REFIN1  
Self-bias voltage of  
Self-biased1  
kΩ  
kΩ  
Input Resistance,  
Self-biased1  
4.4  
5.3  
6.4  
Dual Single-Ended Mode (REF1, REF2)  
Input Frequency (AC-Coupled)  
Input Frequency (DC-Coupled)  
Input Sensitivity (AC-Coupled)  
Input Logic High  
Two single-ended CMOS-compatible inputs  
Slew rate > 50 V/μs  
Slew rate > 50 V/μs; CMOS levels  
Should not exceed VS p-p  
20  
0
250  
250  
MHz  
MHz  
V p-p  
V
0.8  
2.0  
Input Logic Low  
0.8  
V
Input Current  
Pulse Width High/Low  
−100  
1.8  
+100  
μA  
ns  
This value determines the allowable input duty cycle and is the  
amount of time that a square wave is high/low  
Input Capacitance  
2
pF  
REFIN  
Each pin, REFIN/  
(REF1/REF2)  
PHASE/FREQUENCY DETECTOR (PFD)  
PFD Input Frequency  
100  
45  
MHz  
MHz  
ns  
ns  
ns  
Antibacklash pulse width = 1.3 ns, 2.9 ns  
Antibacklash pulse width = 6.0 ns  
Register 0x017[1:0] = 01b  
Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b  
Register 0x017[1:0] = 10b  
Antibacklash Pulse Width  
1.3  
2.9  
6.0  
Rev. B | Page 4 of 64  
 
 
 
1234567...64

下载PDF

与AD9518-4A-PCBZ相关器件

型号 品牌 描述 获取价格 数据表
AD9518-4BCPZ ADI 6-Output Clock Generator with Integrated 1.6 GHz VCO

获取价格
AD9518-4BCPZ-REEL7 ADI 6-Output Clock Generator with Integrated 1.6 GHz VCO

获取价格
AD9520 ADI Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers

获取价格
AD9520-0 ADI 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

获取价格
AD9520-0/PCBZ ADI 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

获取价格
AD9520-0BCPZ ADI 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

获取价格

与AD9518-4A-PCBZ相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证