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AD9389/PCB PDF预览

AD9389/PCB

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
48页 926K
描述
800 MHz High Performance HDMI/DVI Transmitter

AD9389/PCB 数据手册

 浏览型号AD9389/PCB的Datasheet PDF文件第6页浏览型号AD9389/PCB的Datasheet PDF文件第7页浏览型号AD9389/PCB的Datasheet PDF文件第8页浏览型号AD9389/PCB的Datasheet PDF文件第10页浏览型号AD9389/PCB的Datasheet PDF文件第11页浏览型号AD9389/PCB的Datasheet PDF文件第12页 
AD9389  
DESIGN GUIDE  
GENERAL DESCRIPTION  
Table 8. Input Formats Supported  
No. of Bits  
Input Format  
The AD9389 HDMI transmitter provides a high bandwidth digital  
content protected (HDCP) digital link between a wide range of  
digital input formats—both audio and video (see Table 8) and  
output formats (see Table 9). Video and audio data are captured  
and prepared for transmission while two separate I2C buses (one of  
which is a master) are used to program and provide content  
protection for the data to be transmitted.  
12  
12  
24  
24  
16  
20  
24  
8
10  
12  
8
10  
12  
RGB (DDR)  
YCbCr 4:4:4 (DDR)  
RGB 4:4:4  
YCbCr 4:4:4  
YCbCr 4:2:2 (ITU.601)  
YCbCr 4:2:2 (ITU.601)  
YCbCr 4:2:2 (ITU.601)  
YCbCr (DDR)  
YCbCr (DDR)  
YCbCr (DDR)  
YCbCr 4:2:2 (ITU.656)  
YCbCr 4:2:2 (ITU.656)  
YCbCr 4:2:2 (ITU.656)  
VIDEO DATA CAPTURE  
The AD9389 can accept video data from as few as eight pins  
(YCbCr DDR) representing 8-bit data or as many as 24 pins  
representing 12-bit data. The AD9389 is capable of detecting  
all of the 34 video formats defined in the EIA/CEA-861B  
specification. If video ID (VID) 32, 33, or 34 is present, the user  
needs to set Register 0x15[0] to 0b1, as these modes have VREF  
frequencies of 30 Hz or less. The user can read the detected  
video format at 0x3E[7:2]. Formats outside the EIA/CEA-861B  
specification can be read in 0x3F[7:5]. Detailed line count  
differences for 240p and 288p modes can be read from  
0x3F[4:3]. In order to distinguish between an aspect ratio of 4:3  
and one of 16:9, 0x17[1] should be set accordingly.  
Table 9. Output Formats Supported  
No. of Bits  
Output Format  
24  
24  
16  
20  
24  
RGB 4:4:4  
YCbCr 4:4:4  
YCbCr 4:2:2  
YCbCr 4:2:2  
YCbCr 4:2:2  
INPUT FORMATS  
tSETUP  
INPUT CLOCK-  
RISING EDGE  
tHOLD  
INPUT DATA:  
D(23:0), DE, SYNCS  
tHOLD  
tHOLD  
tSETUP  
Figure 3. Timing for Data Input  
Rev. 0 | Page 9 of 48  
 
 
 

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