Datasheet > AD9389/PCB

AD9389/PCB

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
48页	926K
描述
800 MHz High Performance HDMI/DVI Transmitter

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数据手册

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AD9389/PCB 数据手册

AD9389

Pin Type

Pin No.

Mnemonic

Tx0+

Tx0−

Description

Value

31, 30

Differential Output Channel 0

Differential Output Channel 0 Complement

Interrupt

TMDS

INT

1.8 V CMOS

POWER SUPPLY

24, 29, 36, 41

1, 61, 62, 63, 64

16, 19, 20, 21

15, 17, 18, 22,

26, 32, 39, 42,

43, 59, 60, 79,

AV_DD

DV_DD

PV_DD

GND

Output Power Supply

Digital and I/O Power Supply

PLL Power Supply

Ground

1.8 V

0 V

CONTROL

SDA

SCL

DDSDA

DDCSCL

Serial Port Data I/O

3.3 V CMOS

Serial Port Data Clock (100 kHz Maximum)

Serial Port Data I/O to Receiver

Serial Port Data Clock to Receiver

No Connect.

NO CONNECT

48, 49

Table 5. Pin Function Descriptions

Pin Mnemonic

Description

OUTPUTS

TxC+

TxC−

Differential Clock Output at Pixel Clock Rate; Transition Minimized Differential Signaling (TMDS).

Differential Clock Output Complement.

Tx2+

Tx2−

Differential Output of the Red Data at 10× the Pixel Clock Rate; TMDS.

Differential Red Output Complement.

Tx1+

Tx1−

Differential Output of the Green Data at 10× the Pixel Clock Rate; TMDS.

Differential Green Output Complement.

Tx0+

Tx0−

Differential Output of the Blue Data at 10× the Pixel Clock Rate; TMDS.

Differential Blue Output Complement.

INT

Interrupt.

SERIAL PORT (2-WIRE)

SDA

Serial Port Data I/O.

SCL

Serial Port Data Clock.

DDSDA

DDCSCL

Serial Port Data I/O Master to Receiver.

Serial Port Data Clock Master to Receiver.

For a full, functional description of the 2-wire serial register, refer to the 2-Wire Serial Control Port section.

INPUTS

D[23:0]

CLK

Digital Input in RGB or YCbCr Format.

Video Clock Input.

Data Enable for Video Data.

HSYNC

VSYNC

EXT_SW

HPD

S/PDIF

MCLK

I²S[3:0]

I²S CLK

LRCLK

PD/A0

Horizontal Sync Input.

Vertical Sync Input. This is the input for vertical sync.

Place an 887 Ω resistor (1% tolerance) between this pin and ground.

Hot Plug Detect. This indicates to the interface whether the receiver is connected.

S/PDIF Audio Input. This is the audio input from a Sony/Philips Digital Interface.

Audio Reference Clock. Can be set from 128 × f_Sto 512 × f_S.

I²S Audio Inputs. These represent the eight channels of audio (two per input) available through I²S.

I²S Audio Clock.

Left/Right Channel Selection.

Power Down.

Rev. 0 | Page 7 of 48

1...4 5 678 9 10...48

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