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AD8567ACP PDF预览

AD8567ACP

更新时间: 2024-01-04 08:33:15
品牌 Logo 应用领域
亚德诺 - ADI 运算放大器
页数 文件大小 规格书
12页 151K
描述
16 V Rail-to-Rail Operational Amplifiers

AD8567ACP 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:0.93
Is Samacsys:N放大器类型:OPERATIONAL AMPLIFIER
架构:VOLTAGE-FEEDBACK最大平均偏置电流 (IIB):0.8 µA
25C 时的最大偏置电流 (IIB):0.6 µA标称共模抑制比:95 dB
频率补偿:YES最大输入失调电压:10000 µV
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:5 mm低-偏置:NO
低-失调:NO微功率:NO
湿度敏感等级:1功能数量:4
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
功率:NO电源:4.5/16 V
可编程功率:NO认证状态:Not Qualified
座面最大高度:1.2 mm最小摆率:4 V/us
标称压摆率:6 V/us子类别:Operational Amplifier
最大压摆率:4 mA供电电压上限:18 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30标称均一增益带宽:5000 kHz
最小电压增益:3000宽带:NO
宽度:4.4 mmBase Number Matches:1

AD8567ACP 数据手册

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AD8565/AD8566/AD8567  
APPLICATIONS  
Theory of Operation  
The benefit of this type of input stage is low bias current. The  
input bias current is the sum of base currents of Q4Q5 and  
Q6Q8 over the range from (VNEG + 1 V) to (VPOS 1 V). Outside  
of this range, input bias current is dominated by the sum of base  
current of Q10Q11 for input signals close to VNEG and of Q6Q8  
(Q10Q11) for signal close to VPOS. From this type of design,  
the input bias current of AD856x not only exhibits different  
amplitude, but also exhibits different polarities. Figure 2 provides  
the characteristics of the input bias current versus common-mode  
voltage. It is important to keep in mind that the source impedances  
driving the AD856x inputs are balanced for optimum dc and ac  
performance.  
The AD856x family is designed to drive large capacitive loads in  
LCD applications. It has high output current drive, rail-to-rail  
input/output operation and is powered from a single 16 V supply.  
It is also intended for other applications where low distortion and  
high output current drive are needed.  
Figure 1 illustrates a simplified equivalent circuit for the AD856x.  
The rail-to-rail bipolar input stage is composed of two PNP  
differential pairs, Q4Q5 and Q10Q11, operating in series with  
diode protection networks, D1D2. Diode network D1D2  
serves as protection against large transients for Q4Q5, to  
accommodate rail-to-rail input swing. D5D6 protect Q10Q11  
against zenering. In normal operation, Q10Q11 are off and their  
input stage is buffered from the operational amplifier inputs by  
Q6D3 and Q8D4. Operation of the input stage is best understood  
as a function of applied common-mode voltage: When the inputs  
of the AD856x are biased midway between the supplies, the  
differential signal path gain is controlled by resistive loads (Via R9,  
R10) Q4Q5. As the input common-mode level is reduced toward  
the negative supply (VNEG or GND), the input transistor current  
sources, I1 and I2, are forced into saturation, thereby forcing the  
Q6D3 and Q8D4 networks into cutoff; However, Q4Q5 remain  
active, providing input stage gain. Inversely, when common-mode  
input voltage is increased toward the positive supply, Q4Q5 are  
driven into cutoff, Q3 is driven into saturation, and Q4 becomes  
active, providing bias to the Q10Q11 differential pair. The point  
at which Q10Q11 differential pair becomes active is approximately  
equal to (VPOS 1 V).  
1,000  
V
T
= 16V  
= 25C  
S
A
800  
600  
400  
200  
0
200  
400  
600  
800  
1,000  
0
2
4
6
8
10  
12  
14  
16  
INPUT COMMON-MODE VOLTAGE V  
Figure 2. AD856x Input Bias Current vs. Common-Mode  
Voltage  
V
POS  
In order to achieve rail-to-rail output performance, the AD856x  
design uses a complementary common-source (or gmRL) output.  
This configuration allows output voltages to approach the power  
supply rails, particularly if the output transistors are allowed to  
enter the triode region on extremes of signal swing which are  
limited by VGS, the transistor sizes, and output load current.  
Also, this type of output stage exhibits voltage gain in an open-loop  
gain configuration. The amount of gain depends on the total  
load resistance at the output of the AD856x.  
R1  
BIAS LINE  
Q3  
Q4  
D1  
R3  
D2  
R4  
Q6  
Q8  
C1  
V+  
V  
Q5  
Input Overvoltage Protection  
Q4  
As with any semiconductor device, whenever the input exceeds  
either supply voltages, attention needs to be paid to the input  
overvoltage characteristics. As an overvoltage occurs, the amplifier  
could be damaged, depending on the voltage level and the magnitude  
of the fault current. When the input voltage exceeds either supply  
by more than 0.6 V, internal pn junctions will allow current to  
flow from the input to the supplies.  
R5  
R6  
D3  
D4  
C2  
D5  
Q11  
Q10  
I1  
I2  
D6  
This input current is not inherently damaging to the device as  
long as it is limited to 5 mA or less. If a condition exists using  
the AD856x where the input exceeds the supply more than 0.6 V,  
a series external resistor should be added. The size of the resistor  
can be calculated by using the maximum overvoltage divided by  
5 mA. This resistance should be placed in series with either input  
exposed to an overvoltage.  
FOLDED  
CASCADE  
R9  
R10  
V
NEG  
Figure 1. AD856x Equivalent Input Circuit  
REV. A  
8–  

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