AD8400/AD8402/AD8403
SPECIFICATIONS
(VDD = 3 V ꢂ 10% or 5 V ꢂ 10%, VA = VDD, VB = 0 V, –40ꢃC ≤ TA ≤ +125ꢃC unless otherwise noted.)
ELECTRICAL CHARACTERISTICS–50 kꢀ and 100 kꢀ VERSIONS
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL2
Resistor Nonlinearity2
Nominal Resistance3
R-DNL
R-INL
RAB
RAB
∆RAB/∆T
RW
RWB, VA = No Connect
RWB, VA = No Connect
TA = 25°C, Model: AD840XYY50
TA = 25°C, Model: AD840XYY100
VAB = VDD, Wiper = No Connect
IW = 1 V/R
–1
–2
35
70
1/4
1/2
50
100
500
53
+1
+2
65
LSB
LSB
kΩ
130
kΩ
Resistance Tempco
Wiper Resistance
Nominal Resistance Match
ppm/°C
Ω
%
100
1
∆R/RAB
CH 1 to 2, 3, or 4, VAB = VDD, TA = 25°C
0.2
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution
N
INL
8
Bits
Integral Nonlinearity4
Differential Nonlinearity4
–4
–1
–1
–1.5
1
1/4
1/4
1/2
15
–0.25
+0.1
+4
+1
+1
+1.5
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
DNL
DNL
DNL
∆VW/∆T
VWFSE
VWZSE
VDD = 5 V
VDD = 3 V TA = 25°C
V
DD = 3 V TA = –40°C, +85°C
Voltage Divider Tempco
Full-Scale Error
Zero-Scale Error
Code = 80H
Code = FFH
Code = 00H
–1
0
0
+1
RESISTOR TERMINALS
Voltage Range5
VA, B, W
CA, B
CW
IA_SD
RW_SD
0
VDD
V
Capacitance6 Ax, Bx
Capacitance6 Wx
f = 1 MHz, Measured to GND, Code = 80H
f = 1 MHz, Measured to GND, Code = 80H
VA = VDD, VB = 0 V, SHDN = 0
15
80
0.01
100
pF
pF
µA
Ω
Shutdown Current7
Shutdown Wiper Resistance
5
200
VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
VIH
VIL
VIH
VIL
VOH
VOL
IIL
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
RL = 2.2 kΩ to VDD
IOL = 1.6 mA, VDD = 5 V
VIN = 0 V or 5 V, VDD = 5 V
2.4
V
V
V
V
V
V
µA
pF
0.8
0.6
2.1
Output Logic High
Output Logic Low
Input Current
VDD – 0.1
0.4
1
Input Capacitance6
CIL
5
POWER SUPPLIES
Power Supply Range
VDD Range
IDD
IDD
PDISS
PSS
PSS
2.7
5.5
5
4
V
µA
mA
µW
%/%
%/%
Supply Current (CMOS)
Supply Current (TTL)8
Power Dissipation (CMOS)9
Power Supply Sensitivity
VIH = VDD or VIL = 0 V
0.01
0.9
VIH = 2.4 V or 0.8 V, VDD = 5.5 V
VIH = VDD or VIL = 0 V, VDD = 5.5 V
VDD = 5 V 10%
27.5
0.0002 0.001
VDD = 3 V 10%
0.006
0.03
DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB
BW_50K
BW_100K
THDW
R = 50 kΩ
125
71
0.003
9
18
20
kHz
kHz
%
µs
µs
nV/√Hz
nV/√Hz
dB
R = 100 kΩ
Total Harmonic Distortion
VW Settling Time
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, 1% Error Band
VA = VDD, VB = 0 V, 1% Error Band
RWB = 25 kΩ, f = 1 kHz, RS = 0
RWB = 50 kΩ, f = 1 kHz, RS = 0
VA = VDD, VB = 0 V
tS_50K
tS_100K
eNWB_50K
eNWB_100K
CT
Resistor Noise Voltage
29
–65
Crosstalk11
NOTES
11Typicals represent average readings at 25°C and VDD = 5 V.
12Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
1positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See TPC 29 test circuit.
1IW = VDD/R for VDD = 3 V or 5 V for the 50 kΩ and 100 kΩ versions.
13
V
AB
= VDD, Wiper (VW) = No Connect.
14INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
1DNL Specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC 28 test circuit.
15Resistor terminals A, B, W have no limitations on polarity with respect to each other.
16Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
1resistor terminals are left open circuit.
17Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
18Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 20 for a plot of IDD versus logic voltage.
19
P
is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
DISS
10All Dynamic Characteristics use VDD = 5 V.
11Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
Specifications subject to change without notice.
–3–
REV. C