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AD8385ASVZ PDF预览

AD8385ASVZ

更新时间: 2024-02-04 20:27:13
品牌 Logo 应用领域
亚德诺 - ADI 转换器电平转换器接口集成电路驱动
页数 文件大小 规格书
24页 852K
描述
10-Bit, 12-Channel Decimating LCD DECDRIVER with Level Shifters

AD8385ASVZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LEAD FREE, TQFP-100针数:100
Reach Compliance Code:unknown风险等级:5.68
显示模式:SEGMENT接口集成电路类型:INTERFACE CIRCUIT
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
长度:14 mm湿度敏感等级:3
底板数:0-BP功能数量:1
区段数:12端子数量:100
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TFQFP
封装等效代码:TQFP100,.63SQ封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:3.3,15.5 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Other Interface ICs
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:BIPOLAR温度等级:OTHER
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
Base Number Matches:1

AD8385ASVZ 数据手册

 浏览型号AD8385ASVZ的Datasheet PDF文件第7页浏览型号AD8385ASVZ的Datasheet PDF文件第8页浏览型号AD8385ASVZ的Datasheet PDF文件第9页浏览型号AD8385ASVZ的Datasheet PDF文件第11页浏览型号AD8385ASVZ的Datasheet PDF文件第12页浏览型号AD8385ASVZ的Datasheet PDF文件第13页 
AD8385  
Pin Name  
Function  
Description  
SCL  
Serial Interface Data  
Clock  
Clock for the Serial Interface.  
SDI  
Serial Interface Data  
Input  
While the SEN input is low, one 12-bit serial word is loaded into the serial interface on the rising  
edges of SCL. The first four bits select the function; the following eight bits are the data used in the  
serial DACs.  
SEN  
Serial Interface  
Enable  
A falling edge of this input initiates a loading cycle. While this input is held low, the serial interface  
is enabled and data is loaded on every rising edge of SCL. The selected functions are updated on  
the rising edge of this input. While this input is held high, the serial interface is disabled.  
VAO1, VAO2  
TSTM  
Serial DAC Voltage  
Output  
Test Mode  
These output voltages are updated on the rising edge of the SEN input.  
When this input is low, the overload protection and output mode are determined by the function  
programmed into the serial interface. While this input is held high, the overload protection is  
forced to enabled and the output mode is forced to normal, regardless of function programmed  
into the serial interface.  
TSTA  
Test Pin  
Connect this pin to DGND.  
MONITI  
MONITO  
DYIN, DIRYIN,  
DIRXIN, DXIN,  
NRGIN,  
Monitor Input  
Monitor Output  
Inverting Level  
Shifter Inputs  
Logic Input of the Level Shifting Inverting Edge Detector.  
Output of the Level Shifting Inverting Edge Detector.  
Logic Input of the Inverting Level Shifters.  
ENBX(1–4)IN  
DX, DY, DIRX,  
DIRY, NRG,  
ENBX(1–4)  
Inverting Level  
Shifter Outputs  
While the corresponding input voltage of these level shifters is below the threshold voltage, the  
output voltage at these pins is at VOH. While the corresponding input voltage of these level  
shifters is above the threshold voltage, the output voltage at these pins is at VOL.  
CLXIN, CLYIN  
Complementary  
Logic Input of the Complementary Level Shifters.  
Level Shifter Inputs  
CLX, CLXN,  
CLY, CLYN,  
Complementary  
Level Shifter  
Outputs  
While the corresponding input voltage of these level shifters is below the threshold voltage, the  
voltage at the noninverting output pins is at VOH and the voltage at the inverting outputs is at  
VOL. While the corresponding input voltage of these level shifters is above the threshold voltage,  
the voltage at the noninverting output pins is at VOL and the voltage at the inverting outputs is at  
VOH.  
Rev. 0 | Page 10 of 24  

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