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AD8382 PDF预览

AD8382

更新时间: 2024-01-16 14:35:38
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 868K
描述
High Performance 12-Bit, 6-Channel Output, Decimating LCD DecDriver

AD8382 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFN
包装说明:7 X 7 MM, MO-220-VKKD-2, LFCSP-48针数:48
Reach Compliance Code:unknown风险等级:5.77
数据输入模式:PARALLEL接口集成电路类型:LIQUID CRYSTAL DISPLAY DRIVER
JESD-30 代码:S-PQCC-N48JESD-609代码:e0
长度:7 mm湿度敏感等级:NOT SPECIFIED
复用显示功能:NO功能数量:1
区段数:6端子数量:48
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:COMMERCIAL
座面最大高度:1 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
电源电压1-最大:18 V电源电压1-分钟:9 V
电源电压1-Nom:15.5 V表面贴装:YES
温度等级:OTHER端子面层:TIN LEAD
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

AD8382 数据手册

 浏览型号AD8382的Datasheet PDF文件第17页浏览型号AD8382的Datasheet PDF文件第18页浏览型号AD8382的Datasheet PDF文件第19页浏览型号AD8382的Datasheet PDF文件第21页浏览型号AD8382的Datasheet PDF文件第22页浏览型号AD8382的Datasheet PDF文件第23页 
AD8382  
POWER SUPPLY BYPASSING  
Layout Considerations  
All power supply and reference pins of the AD8382 must be  
properly bypassed to the analog ground plane for optimum  
performance.  
The AD8382 is a mixed-signal, high speed, high accuracy  
device. In order to fully realize its specifications, it is essential to  
use a properly designed printed circuit board.  
All analog supply pins may be connected directly to an analog  
supply plane located as close to the part as possible. A 0.1 µF  
chip capacitor should be placed as close to each analog supply  
pin as possible and connected directly between each analog  
supply pin and the analog ground plane.  
LAYOUT AND GROUNDING  
The analog outputs and the digital inputs of the AD8382 are on  
opposite sides of the package. Keep these sections separated to  
minimize crosstalk and coupling of digital inputs into the  
analog outputs.  
A minimum 47 µF tantalum capacitor should be placed near the  
analog supply plane and connected directly between the supply  
and analog ground planes.  
All signal trace lengths should be made as short and direct as  
possible to prevent signal degradation due to parasitic effects.  
Note that digital signals should not cross and should not be  
routed near analog signals.  
A minimum 10 µF tantalum capacitor should be placed near the  
digital supply pin and connected directly to the analog ground  
plane. A 0.1 µF chip capacitor should be connected between the  
digital supply pin and the analog ground.  
It is imperative to provide a solid analog ground plane under  
and around the AD8382. All ground pins of the part should be  
connected directly to this ground plane with no extra signal  
path length. This includes DGND, AGNDBIAS, AGND5,  
AGND3,4, AGND1,2, AGND0, and AGNDDAC. The return  
traces for any of the signals should be routed close to the  
ground pin for that section to prevent stray signals from  
coupling into other ground pins.  
VREFHI, VREFLO, V2, V1 REFERENCE  
DISTRIBUTION  
To ensure well-matched video outputs, all AD8382s must  
operate from equal reference voltages.  
Each reference voltage should be distributed to each AD8382  
directly from the source of the reference voltage with  
approximately equal trace lengths.  
A 0.1 µF chip capacitor should be placed as close to each  
reference input pin as possible and directly connected between  
the reference input pin and the analog ground plane.  
Rev. 0 | Page 20 of 24  
 

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