5秒后页面跳转
AD8345 PDF预览

AD8345

更新时间: 2024-01-21 07:15:13
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
16页 369K
描述
250 MHz.1000 MHz Quadrature Modulator

AD8345 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ActiveReach Compliance Code:unknown
风险等级:5.58Is Samacsys:N
特性阻抗:50 Ω构造:COMPONENT
最大输入功率 (CW):10 dBmJESD-609代码:e3
调制技术:QUADRAPHASE最大工作频率:1000 MHz
最小工作频率:140 MHz最高工作温度:85 °C
最低工作温度:-40 °C射频/微波设备类型:MODULATOR
端子面层:MATTE TINBase Number Matches:1

AD8345 数据手册

 浏览型号AD8345的Datasheet PDF文件第6页浏览型号AD8345的Datasheet PDF文件第7页浏览型号AD8345的Datasheet PDF文件第8页浏览型号AD8345的Datasheet PDF文件第10页浏览型号AD8345的Datasheet PDF文件第11页浏览型号AD8345的Datasheet PDF文件第12页 
AD8345  
IP  
IN  
AD8345  
1
2
3
4
5
6
7
8
QP  
QN  
16  
QBBP  
IBBP  
IBBN  
COM3  
COM1  
LOIN  
LOIP  
QBBN 15  
14  
13  
12  
11  
10  
9
COM3  
COM3  
VPS2  
VOUT  
COM2  
COM3  
C6  
1000pF  
5
4
1
2
3
+V  
LO  
S
C1  
C2  
0.01F  
T1  
R1  
50⍀  
C7  
1000pF  
1000pF  
ETC1-1-13  
VOUT  
C5  
1000pF  
VPS1  
ENBL  
+V  
S
C4  
0.01F  
C3  
1000pF  
Figure 3. Basic Connections  
5  
BASIC CONNECTIONS  
The basic connections for operating the AD8345 are shown in  
Figure 3. A single power supply of between 2.7 V and 5.5 V is  
applied to pins VPS1 and VPS2. A pair of ESD protection diodes  
are connected internally between VPS1 and VPS2 so these must  
be tied to the same potential. Both pins should be individually  
decoupled using 1000 pF and 0.01 µF capacitors, located as  
close as possible to the device. For normal operation, the enable  
pin, ENBL, must be pulled high. The turn-on threshold for  
ENBL is VS/2. Pins COM1 to COM3 should all be tied to the  
same low impedance ground plane.  
10  
15  
20  
25  
30  
35  
40  
45  
50  
55  
60  
V
= 5V, DIFFERENTIAL INPUT = 1.2V  
S
LO Drive  
In Figure 3, a 50 resistor to ground combines with the device’s  
high input impedance to provide an overall input impedance of  
approximately 50 (see TPC 17 for a plot of LO port input  
impedance). For maximum LO suppression at the output, a  
differential LO drive is recommended. In Figure 3, this is  
achieved using a balun (M/A-COM Part Number ETC1-1-13).  
40 60 80 100 120 140 160 180 200 220 240 260 280 300  
LO FREQUENCY MHz  
Figure 4. Typical Lower Frequency Sideband Suppression  
Performance  
Baseband I and Q Channel Drive  
The output of the balun is ac coupled to the LO inputs which  
have a bias level about 1.8 V dc. An LO drive level of –2 dBm is  
recommended for lowest output noise. Higher levels will degrade  
linearity while lower levels will tend to increase the noise floor  
slightly. For example, reducing the LO power from –2 dBm to  
–10 dBm will increase the noise floor by approximately 0.3 dB  
(see TPC 19).  
The I and Q channel baseband inputs should be driven differen-  
tially. This is convenient as most modern high-speed DACs  
have differential outputs. For optimal performance at VS = 5 V,  
the drive signal should be a 1.2 V p-p differential signal with a  
bias level of 0.7 V; that is, each input should swing from 0.4 V  
to 1 V. If the AD8345 is being run on a lower supply voltage,  
the peak-to-peak voltage on the I and Q channel inputs must be  
reduced to avoid input clipping. For example, at a supply volt-  
age of 2.7 V, a 200 mV p-p differential drive is recommended.  
This will result in a corresponding reduction in output power  
(see TPC 1). The I and Q inputs have a large input bandwidth  
of approximately 80 MHz. At lower baseband input levels, the  
input bandwidth increases (see TPC 2).  
The LO terminal can be driven single-ended at the expense of  
slightly higher LO leakage. LOIN is ac coupled to ground using  
a capacitor and LOIP is driven through a coupling capacitor  
from a (single-ended) 50 source (this scheme could also be  
reversed with the drive signal being applied to LOIN).  
LO Frequency Range  
The frequency range on the LO input is limited by the internal  
quadrature phase splitter. The phase splitter generates drive  
signals for the internal mixers which are 90° out of phase relative  
to one another. Outside of the specified LO frequency range of  
250 MHz to 1 GHz, this quadrature accuracy degrades, result-  
ing in decreased sideband suppression. See TPC 9 for a plot of  
sideband suppression vs. LO frequency from 250 MHz to 1 GHz.  
Figure 4 shows the sideband suppression of a typical device  
from 50 MHz to 300 MHz. The level of sideband suppression  
degradation below 250 MHz will be subject to manufacturing  
process variations.  
If the baseband signal has a high peak-to-average ratio (e.g.,  
CDMA or WCDMA), the rms signal strength will have to be  
backed off from this peak level in order to prevent clipping of  
the signal peaks. Clipping of signal peaks will tend to increase  
signal leakage into adjacent channels. Backing off the I and Q  
signal strength in the manner recommended will reduce the output  
power by a corresponding amount. This also applies to multicarrier  
applications where the per-carrier output power will be lower by  
3 dB for each doubling of the number of output carriers.  
REV. 0  
–9–  

与AD8345相关器件

型号 品牌 描述 获取价格 数据表
AD8345ARE ADI 250 MHz.1000 MHz Quadrature Modulator

获取价格

AD8345ARE-REEL ADI 250 MHz.1000 MHz Quadrature Modulator

获取价格

AD8345ARE-REEL7 ADI 250 MHz.1000 MHz Quadrature Modulator

获取价格

AD8345AREZ ADI 140 MHz to 1000 MHz Quadrature Modulator

获取价格

AD8345AREZ-REEL7 ADI 140MHz - 1000MHz RF/MICROWAVE QUADRAPHASE MODULATOR, MO-153ABT, TSSOP-16

获取价格

AD8345AREZ-RL7 ADI 140 MHz to 1000 MHz Quadrature Modulator

获取价格