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AD8343ARU-REEL

更新时间: 2024-02-15 17:26:36
品牌 Logo 应用领域
亚德诺 - ADI 射频和微波射频混频器微波混频器局域网
页数 文件大小 规格书
27页 393K
描述
DC-to-2.5 GHz High IP3 Active Mixer

AD8343ARU-REEL 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active包装说明:TSSOP14,.25
针数:14Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:0.6特性阻抗:50 Ω
构造:COMPONENTJESD-609代码:e3
安装特点:SURFACE MOUNT端子数量:14
最大工作频率:2500 MHz最小工作频率:
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装等效代码:TSSOP14,.25
电源:5 V射频/微波设备类型:DOUBLE BALANCED
子类别:RF/Microwave Mixers最大压摆率:75 mA
表面贴装:YES技术:BIPOLAR
端子面层:Matte Tin (Sn)最大电压驻波比:2
Base Number Matches:1

AD8343ARU-REEL 数据手册

 浏览型号AD8343ARU-REEL的Datasheet PDF文件第18页浏览型号AD8343ARU-REEL的Datasheet PDF文件第19页浏览型号AD8343ARU-REEL的Datasheet PDF文件第20页浏览型号AD8343ARU-REEL的Datasheet PDF文件第22页浏览型号AD8343ARU-REEL的Datasheet PDF文件第23页浏览型号AD8343ARU-REEL的Datasheet PDF文件第24页 
AD8343  
R1A and R1B set the core bias current of 18.5 mA per side. L1A  
and L1B provide the RF choking required to avoid shunting the  
signal. Z1, Z2A, and Z2B comprise a typical input matching net-  
work that is designed to match the AD8343s differential input  
impedance to the differential output impedance of the balun.  
R1A and R1B set the core bias current of 18.5 mA per side. Z1,  
Z2A, and Z2B comprise a typical input matching network that  
is designed to match the AD8343s differential input impedance  
to the differential output impedance of the balun. It was assumed  
for this example that the input frequency is low and that the  
magnitude of the devices input impedance is therefore much  
smaller than the bias resistor values, allowing the input bias  
inductors to be eliminated with very little penalty in gain or  
noise performance.  
The IF output is taken through a 4:1 (impedance ratio) trans-  
former that reflects a 200 differential load to the collectors.  
This output coupling arrangement is reasonably broadband,  
although in some cases the user might want to consider adding a  
resonator tank circuit between the collectors to provide a mea-  
sure of IF selectivity. The ferrite bead (FB), in series with the  
output transformers center tap, addresses the common-mode  
stability concern.  
In this example, the output signal is taken via a differential  
matching network comprising Z3 and Z4A/B, then through the  
1:1 balun and dc blocking capacitors to the single-ended output.  
The output frequency is assumed to be high enough that conju-  
gate matching to the output of the AD8343 is desirable, so the  
goal of the matching network is to provide a conjugate match  
between the devices output and the differential input of the  
output balun.  
In this circuit the PWDN pin is shown connected to GND,  
which enables the mixer. In order to enter power-down mode  
and conserve power, the PWDN pin should be taken within  
500 mV of VPOS.  
This circuit uses shunt feed to provide collector bias for the  
transistors because the output balun in this circuit has no con-  
venient center-tap. The ferrite beads, in series with the outputs  
bias inductors, provide some small degree of damping to ease  
the common-mode stability problem. Unfortunately this type of  
output balun may present a common-mode load that enters the  
region of output instability, so most of the burden of avoiding  
overt instability falls on the input circuit, which should present  
an inductive common-mode termination over as broad a band of  
frequencies as possible.  
The DCPL pin should be bypassed to GND with about 0.1 µF.  
Failure to do so could result in a higher noise level at the output  
of the device.  
Upconverting Mixer  
A typical upconversion application is shown in Figure 22. Both  
the input and output single-ended-to-differential conversions  
are obtained through the use of 1:1 transmission line baluns.  
The differential input and output matching networks are designed  
between the balun and the I/O pins of the AD8343. The local  
oscillator signal at a level of 12 dBm to 3 dBm is brought in  
through a third 1:1 balun.  
The PWDN pin is shown as tied to GND, which enables the  
mixer. The DCPL pin should be bypassed to GND with about  
0.1 µF in order to bypass noise from the internal bias circuit.  
V
POS  
V
POS  
0.1F  
FB  
VPOS  
COMM  
OUTP  
Z4  
0.1F  
RF  
A
OUT  
DCPL  
Z3  
BIAS  
PWDN  
OUTM  
Z4  
B
0.1F  
0.1F  
LOIP  
LOIM  
FB  
LO IN  
V
POS  
AD8343  
Z1  
INPP  
INPM  
Z2  
Z2  
R
A
FIN  
B
R1  
A
R1  
B
Figure 22. Typical Upconversion Application  
–21–  
REV. 0  

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