Datasheet > 射频和微波 > 射频/微波调制器/解调器> AD8339ACPZ

AD8339ACPZ

更新时间： 2024-01-15 02:03:05

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
15页	237K
描述
DC to 50 MHz, Quad I/Q Demodulator and Phase Shifter

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AD8339ACPZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	针数：	40
Reach Compliance Code：	compliant	ECCN代码：	5A991.B
HTS代码：	8542.39.00.01	风险等级：	5.8
特性阻抗：	50 Ω	构造：	COMPONENT
最大输入功率 (CW)：	13 dBm	JESD-609代码：	e3
调制技术：	I/Q	最大工作频率：	50 MHz
最小工作频率：		最高工作温度：	85 °C
最低工作温度：	-40 °C	射频/微波设备类型：	DEMODULATOR
端子面层：	Matte Tin (Sn)

AD8339ACPZ 数据手册

AD8339

Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RF2N

RF2P

COMM

SCLK

CSB

30 Q2OP

Pin 1

Identifier

29 I2OP

28 VPOS

27 VPOS

26 4LOP

25 4LON

24 VNEG

23 VNEG

22 I3OP

21 Q3OP

AD8339

Top View

VPOS

RF3P

(not to scale)

RF3N 10

Figure 2. 40-Lead LFCSP

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

RF1P-RF4P

RF1N-RF4N

Description

1, 2, 9, 10,

13, 14, 37,

RF Inputs. No internal bias. The optimum common mode voltage for maximum symmetrical input differential

swing is 2.5 V if ±5 V supplies are used.

3, 4, 15, 36 COMM

Ground

SCLK

CSB

Serial Interface – Clock

Serial Interface – Chip Select Bar. Active Low.

7, 8, 11,

16, 27, 28,

VPOS

Positive Supply. These pins should be decoupled with a ferrite bead in series with the supply, plus a 0.1 μF

and 1 nF capacitor between the VPOS pins and ground. Since the VPOS pins are internally connected, one set

of supply decoupling components on each side of the chip should be sufficient.

SDO

LODC

Serial Interface – Data Output. Normally connected to SDI of next chip or left open.

Decoupling Pin for LO. A 0.1 μF capacitor should be connected between this pin and ground. Value of cap

does influence chip enable/disable times.

18, 19, 21, I1OP-I4OP,

22, 29, 30, Q1OP-Q4OP

32, 33

I/Q Outputs. These outputs provide a bidirectional current that can be converted back to a voltage via a

transimpedance amplifier. Multiple outputs can be summed together through simply connecting them

(Wire-OR). The bias voltage should be set to 0 V or less by the transimpedance amplifier, see Figure 7.

20, 23, 24, VNEG

Negative Supply. These pin should be decoupled with a ferrite bead in series with the supply, plus a 0.1 μF

and 1 nF capacitor between the pin and ground. Since the VNEG pins are internally connected, one set of

supply decoupling components should be sufficient.

25, 26

4LOP, 4LON

LO Inputs. No internal bias; optimally biased by an LVDS driver. For best performance, these inputs should be

driven differentially.

RSET

SDI

LO Interface - Reset. Logic threshold is at about 1.1 V and therefore can be driven by >1.8 V CMOS logic.

Serial Interface – Data Input. Logic threshold is at about 1.1 V and therefore can be driven by >1.8 V CMOS

logic.

RSTS

Reset for SPI Interface. Logic threshold is at about 1.1 V and therefore can be driven by >1.8 V CMOS logic. For

quick testing without the need to program the SPI, the voltage on the RSTS pin should be pulled to -1.4 V;

this enables all four channels in the Phase (I=1,Q=0) state.

Rev. PrA | Page 6 of 15

1...3 4 567 8 9...15

下载PDF

与AD8339ACPZ相关器件

型号	品牌	描述	获取价格	数据表
AD8339ACPZ-R7	ADI	DC to 50 MHz, Quad I/Q Demodulator and Phase Shifter	获取价格
AD834	ADI	500 MHz Four-Quadrant Multiplier	获取价格
AD834_12	ADI	500 MHz Four-Quadrant Multiplier	获取价格
AD8340	ADI	700 MHz to 1000 MHz RF Vector Modulator	获取价格
AD8340ACP	ADI	IC TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, QCC24, LFCSP-24, Cellular Telephone Circuit	获取价格
AD8340ACPZ-REEL7	ADI	700 MHz to 1000 MHz RF Vector Modulator	获取价格

与AD8339ACPZ相关文章

PCF8574资料解读：主要参数分析、引脚说明
2024-05-21

7
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
2024-05-21

7
ADUM1201资料手册解读：参数分析、引脚说明、应用分析
2024-05-21

10
一文带你了解压敏电阻器在直流电路中的过压保护作用
2024-05-21

5

产品中心

服务支持

精选活动

关于我们

帮助中心

AD8339ACPZ

AD8339ACPZ 技术参数

AD8339ACPZ 数据手册

与AD8339ACPZ相关器件

与AD8339ACPZ相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD8339ACPZ

AD8339ACPZ 技术参数

AD8339ACPZ 数据手册

与AD8339ACPZ相关器件

与AD8339ACPZ相关文章

您还可以找

您在本页遇到什么问题？