AD8324
APPLICATIONS
that uses 8-bits to program the cable driver, the 2 MSBs will be
ignored. This allows the AD8324 to be compatible with some
existing system designs.
GENERAL APPLICATIONS
The AD8324 is primarily intended for use as the upstream
power amplifier (PA) in DOCSIS (data over cable service
interface specification) certified cable modems and CATV set-
top boxes. The upstream signal is either a QPSK or QAM signal
generated by a DSP, a dedicated QPSK/QAM modulator, or a
DAC. In all cases, the signal must be low-pass filtered before
being applied to the PA in order to filter out-of-band noise and
higher order harmonics from the amplified signal.
The AD8324 recognizes gain codes 1 through 60 (all gain codes
are in decimal, unless otherwise noted). When the AD8324 is
programmed with 61 to 63, it will internally default to max gain
(gain code 60). If the programmed gain code is above 63, the
AD8324 will recognize only the 6 LSBs. For example, gain code
75 (01001011 binary) will be interpreted as gain code 11
(001011 binary) since the 2 MSBs are ignored.
Due to the varying distances between the cable modem and the
head-end, the upstream PA must be capable of varying the
output power by applying gain or attenuation. The ability to
vary the output power of the AD8324 ensures that the signal
from the cable modem will have the proper level once it arrives
at the head-end. The upstream signal path commonly includes a
diplexer and cable splitters. The AD8324 has been designed to
overcome losses associated with these passive components in
the upstream cable path.
The programming range of the AD8324 is from –25.5 dB (gain
code 1) to +33.5 dB (gain code 60). The 60 dB gain range is
linear with a 1 dB change in a 1 LSB change in gain code.
Figure 15 illustrates the gain step size of the AD8324 versus gain
code. The AD8324 was characterized with a differential input
signal and a TOKO 458PT-1457 1:1 transformer at the output.
INPUT BIAS, IMPEDANCE, AND TERMINATION
The VIN+ and VIN– inputs have a dc bias level of VCC/2; therefore
the input signal should be ac-coupled as seen in the typical
application circuit (Figure 23). The differential input impedance
of the AD8324 is approximately 1.1 kΩ, while the single-ended
input is 550 Ω. The high input impedance of the AD8324 allows
flexibility in termination and properly matching filter networks.
The AD8324 will exhibit optimum performance when driven
with a pure differential signal.
CIRCUIT DESCRIPTION
The AD8324 is composed of three analog functions in the
transmit-enable mode. The input amplifier (preamp) can be
used in a single-ended or differential configuration. If the input
is used in the differential configuration, the input signals should
be 180 degrees out of phase and of equal amplitude. A vernier is
used in the input stage for controlling the fine 1 dB gain steps.
This stage then drives a DAC, which provides the bulk of the
AD8324’s attenuation. The signals in the preamp and DAC
blocks are differential to improve the PSRR and linearity. A
differential current is fed from the DAC into the output stage.
The output stage maintains 75 Ω differential output impedance
in all power modes.
OUTPUT BIAS, IMPEDANCE, AND TERMINATION.
The output stage of the AD8324 requires a bias of 3.3 V. The
3.3 V power supply should be connected to the center tap of the
output transformer. Also, the VCC that is being applied to the
center tap of the transformer should be decoupled as seen in the
typical application circuit (Figure 23).
GAIN PROGRAMMING FOR THE AD8324
The output impedance of the AD8324 is 75 Ω, regardless of
whether the amplifier is in transmit enable, transmit disable, or
sleep mode. This, when combined with a 1:1 voltage ratio trans-
former, eliminates the need for external back termination resis-
tors. If the output signal is being evaluated using standard 50 Ω
test equipment, a minimum loss 75 Ω to 50 Ω pad must be used
to provide the test circuit with the proper impedance match.
The AD8324 evaluation board provides a convenient means to
implement a matching attenuator. Soldering a 43.3 Ω resistor in
the R15 placeholder and an 86.6 Ω resistor in the R16 place-
holder will allow testing on a 50 Ω system. When using a
matching attenuator, it should be noted that there will be 5.7 dB
of power loss (7.5 dB voltage) through the network.
The AD8324 features a serial peripheral interface (SPI) for
programming the gain code settings. The SPI interface consists
DATEN
of three digital data lines: CLK,
, and SDATA. The
DATEN
pin should be held low while the AD8324 is being
programmed. The SDATA pin accepts the serial data stream for
programming the AD8324 gain code. The CLK pin accepts the
clock signal to latch in the data from the SDATA line.
The AD8324 utilizes a 6-bit shift register for clocking in the
data. The shift register is designed to be programmed MSB first.
The timing interface for programming the AD8324 can be seen
DATEN
in Table 2, Table 3, Figure 3, and Figure 4. While the
pin
is held low, the serial bits on the SDATA line are shifted into the
register on the rising edge of the CLK pin. For existing software
Rev. 0 | Page 10 of 16
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