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AD8317-EVALZ PDF预览

AD8317-EVALZ

更新时间: 2024-02-14 06:24:23
品牌 Logo 应用领域
亚德诺 - ADI 控制器
页数 文件大小 规格书
20页 782K
描述
1 MHz to 10 GHz, 55 dB Log Detector/Controller

AD8317-EVALZ 技术参数

Source Url Status Check Date:2013-05-01 14:56:25.48是否无铅: 含铅
是否Rohs认证: 符合生命周期:Active
零件包装代码:DIE包装说明:DIE,
针数:0Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.73Is Samacsys:N
模拟集成电路 - 其他类型:LOG OR ANTILOG AMPLIFIER标称带宽:10000 MHz
JESD-30 代码:R-XUUC-N8湿度敏感等级:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:RECTANGULAR封装形式:UNCASED CHIP
峰值回流温度(摄氏度):260认证状态:Not Qualified
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BIPOLAR温度等级:INDUSTRIAL
端子形式:NO LEAD端子位置:UPPER
处于峰值回流温度下的最长时间:30Base Number Matches:1

AD8317-EVALZ 数据手册

 浏览型号AD8317-EVALZ的Datasheet PDF文件第7页浏览型号AD8317-EVALZ的Datasheet PDF文件第8页浏览型号AD8317-EVALZ的Datasheet PDF文件第9页浏览型号AD8317-EVALZ的Datasheet PDF文件第11页浏览型号AD8317-EVALZ的Datasheet PDF文件第12页浏览型号AD8317-EVALZ的Datasheet PDF文件第13页 
AD8317  
THEORY OF OPERATION  
The AD8317 is a 6-stage demodulating logarithmic amplifier,  
specifically designed for use in RF measurement and power  
control applications at frequencies up to 10 GHz. A block  
diagram is shown in Figure 21. Sharing much of its design  
with the AD8318 logarithmic detector/controller, the AD8317  
maintains tight intercept variability vs. temperature over a 50 dB  
range. Additional enhancements over the AD8318, such as a  
reduced RF burst response time of 6 ns to 10 ns, 22 mA supply  
current, and board space requirements of only 2 mm × 3 mm,  
add to the low cost and high performance benefits of the AD8317.  
compensate for errors due to internal noise. The common pin,  
COMM, provides a quality low impedance connection to the  
printed circuit board (PCB) ground. The package paddle, which  
is internally connected to the COMM pin, should also be grounded  
to the PCB to reduce thermal impedance from the die to the PCB.  
The logarithmic function is approximated in a piecewise fashion  
by six cascaded gain stages. (For a more comprehensive expla-  
nation of the logarithm approximation, see the AD8307 data  
sheet.) The cells have a nominal voltage gain of 9 dB each and a  
3 dB bandwidth of 10.5 GHz. Using precision biasing, the gain  
is stabilized over temperature and supply variations. The overall  
dc gain is high, due to the cascaded nature of the gain stages. An  
offset compensation loop is included to correct for offsets  
within the cascaded cells. At the output of each of the gain  
stages, a square-law detector cell is used to rectify the signal.  
VPOS  
TADJ  
GAIN  
BIAS  
SLOPE  
VSET  
I
V
VOUT  
CLPF  
I
V
DET  
DET  
DET  
DET  
The RF signal voltages are converted to a fluctuating differential  
current having an average value that increases with signal level.  
Along with the six gain stages and detector cells, an additional  
detector is included at the input of the AD8317, providing a  
50 dB dynamic range in total. After the detector currents are  
summed and filtered, the following function is formed at the  
summing node:  
INHI  
INLO  
COMM  
Figure 21. Block Diagram  
A fully differential design, using a proprietary, high speed SiGe  
process, extends high frequency performance. Input INHI receives  
the signal with a low frequency impedance of nominally 500 ꢀ  
in parallel with 0.7 pF. The maximum input with 1 dB log-  
conformance error is typically 0 dBm (re: 50 ꢀ). The noise  
spectral density referred to the input is 1.15 nV/Hz, which is  
equivalent to a voltage of 118 μV rms in a 10.5 GHz bandwidth  
or a noise power of −66 dBm (re: 50 ꢀ). This noise spectral  
density sets the lower limit of the dynamic range. However,  
the low end accuracy of the AD8317 is enhanced by specially  
shaping the demodulating transfer characteristic to partially  
ID × log10(VIN/VINTERCEPT  
where:  
ID is the internally set detector current.  
)
(1)  
V
V
IN is the input signal voltage.  
INTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT  
,
the output voltage would be 0 V, if it were capable of going to 0 V).  
Rev. B | Page 10 of 20  
 
 

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