AD8315
EVALUATION BOARD
ANTENNA
AD8315
Figure 43 shows the schematic of the AD8315 MSOP evaluation
board. The layout and silkscreen of the component side are
shown in Figure 44 and Figure 45. An evaluation board is also
available for the LFCSP package (see the Ordering Guide for
exact part numbers). Apart from the slightly smaller device
footprint, the LFCSP evaluation board is identical to the MSOP
board. The board is powered by a single supply in the 2.7 V to
5.5 V range. The power supply is decoupled by a single 0.1 μF
capacitor.
C
C
RFIN
STRIPLINE
PA
R
ATTN
C
R
IN
IN
Figure 42. Series Attention Input Coupling Option
Figure 42 shows a third method for coupling the input
signal into the AD8315. A series resistor, connected to the RF
source, combines with the input impedance of the AD8315 to
resistively divide the input signal being applied to the input.
This has the advantage of very little power being tapped off in
RF power transmission applications.
Table 5 details the various configuration options of the
evaluation board.
R2
52.3Ω
C1
0.1µF
TP1
R1
0Ω
AD8315
J1
J2
V
1
8
7
RFIN
RFIN
VPOS
VAPC
NC
POS
R3
0Ω
USING THE CHIP SCALE PACKAGE
J2
V
POS
2
3
4
VAPC
SW1
ENBL
VSET
On the underside of the chip scale package, there is an exposed
paddle. This paddle is internally connected to the chip’s ground.
There is no thermal requirement to solder the paddle down to
the printed circuit board’s ground plane. However, soldering
down the paddle has been shown to increase the stability over
frequency of the AD8315 ACP’s response at low input power
levels (that is, at around −45 dBm) in the DCS and PCS bands.
R4
(OPEN)
C2
(OPEN)
TP2
6
5
VSET
FLTR COMM
C4
(OPEN)
NC = NO CONNECT
LK2
LK1
V
POS
C3
0.1µF
C5
0.1µF
R8
10kΩ
R7
16.2kΩ
AD8031
R6
17.8kΩ
R5
10kΩ
Figure 43. Evaluation Board Schematic (MSOP)
Table 5. Evaluation Board Configuration Options
Component Function
Default Condition
Not Applicable
SW1 = A
TP1, TP2
SW1
Supply anꢀ Grounꢀ Vector Pins.
Device Enable. When in Position A, the ENdL pin is connecteꢀ to VPOS anꢀ the AD8315 is
in operating moꢀe. In Position d, the ENdL pin is grounꢀeꢀ putting the ꢀevice in power-ꢀown moꢀe.
R1, R2
Input Interface. The 52.3 Ω resistor in Position R2 combines with the AD8315’s internal input
impeꢀance to give a broaꢀbanꢀ input impeꢀance of arounꢀ 50 Ω. A reactive match can be
implementeꢀ by replacing R2 with an inꢀuctor anꢀ R1 (0 Ω) with a capacitor. Note that the
AD8315’s RF input is internally ac-coupleꢀ.
R2 = 52.3 Ω (Size 0603)
R1 = 0 Ω (Size 0402)
R3, R4, C2
Output Interface. R4 anꢀ C2 can be useꢀ to check the response of VAPC to capacitive anꢀ resistive
loaꢀing. R3/R4 can be useꢀ to reꢀuce the slope of VAPC.
R4 = C2 = Open (Size 0603)
R3 = 0 Ω (Size 0603)
C1
C4
Power Supply Decoupling. The nominal supply ꢀecoupling consists of a 0.1 μF capacitor.
Filter Capacitor. The response time of VAPC can be moꢀifieꢀ by placing a capacitor between
FLTR (Pin 4) anꢀ grounꢀ.
C1 = 0.1 μF (Size 0603)
C4 = Open (Size 0603)
LK1, LK2
Measurement Moꢀe. A quasimeasurement moꢀe can be implementeꢀ by installing LK1 anꢀ LK2
(connecting an inverteꢀ VAPC to VSET) to yielꢀ the nominal relationship between RFIN anꢀ VSET.
In this moꢀe, a large capacitor (0.01 μF or greater) must be installeꢀ in C4.
LK1, LK2 = Installeꢀ
Rev. C | Page 20 of 24
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